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Explorer
Explorer
10,909 Views
Registered: ‎07-18-2011

Virtex vs. Kintex Fabric Performance

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Hello.

 

Does the FPGA fabric of a Virtex UltraScale device offer any performance advantages over a Kintex UltraScale of comperable size? Or are the differences in the two families just in the peripherals and interfaces (e.g. faster SerDes, faster memory interfaces in the Virtex)?

 

Thank you,

David

 

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Scholar
Scholar
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Registered: ‎02-27-2008

d,

 

Virtex and Kintex Ultrascale+ (16nm) have identical architectures, with the differences being in how many, and of what blocks.

 

The same is true of Ultrascale (20nm), as well as all 7 series devices and families.

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
19,087 Views
Registered: ‎02-27-2008

d,

 

Virtex and Kintex Ultrascale+ (16nm) have identical architectures, with the differences being in how many, and of what blocks.

 

The same is true of Ultrascale (20nm), as well as all 7 series devices and families.

Austin Lesea
Principal Engineer
Xilinx San Jose

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Guide
Guide
10,897 Views
Registered: ‎01-23-2009

Minor clarification...

 

The Artix-7 devices have a slower fabric than the Kintex-7 and Virtex-7 (which are the same).

 

The rest is as @austin said; the fabric performance of the Kintex UltraScale and Virtex UltraScale are the same as eachother, and the Kintex UltraScale+ and Virtex UltraScale+ are the same as eachother (but obviously faster than the UltraScale).

 

There are some differences in certain cell performances (notably the GTX/GTH/GTY... and PCIe) depending on family member and package, but the fabric (LUTs, FFs, BRAMs, DSPs) don't change within the related family members.

 

Avrum

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Scholar
Scholar
10,890 Views
Registered: ‎02-27-2008

a,

 

Correct.  To the extent possible, Artix is optimized for low power, Kintex for best overall (performance, power, cost), and Virtex for best performance.  They all use the same recipe (TSMC HPL process) but there are minor tweaks to the design and process that allow us to differentiate them.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Advisor
Advisor
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Registered: ‎10-10-2014

thanks for the clarifications above @avrumw 

so just to make sure : is my conclusion correct for Zynq UltraScale+ MPSoC devices, that there is no 'subdivision' as in Zynq 7000 devices (Artix/Kintex based)? 

looking at the language templates in Vivado : for use of these templates in Zynq US+ MPSoC devices, that does probably mean I can choose from both the Kintex UltraScale+ and Virtex UltraScale+? (these look to be completely identical anyway)

templates.jpg

 

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