03-25-2021 10:20 AM
I am using High-Speed SelectIO wizard to create RX interface using the IP catalog ip_rx_bank66_inst. External data is coming as input to the FPGA.
At the top level, I have 2 differential pairs which are the RX signal ports that connect to the High-Speed SelectIO IP. When I do implementation in Vivado 2020.1, the High-Speed SelectIO is getting optimize and removed. Ch0_ca_p, Ch0_ca_n are inputs to the High-Speed SelectIO are left dangling. During synthesis, these pins are connected to the ip_rx_bank66_inst.
Please see the attached pictures.
What might be causing Vivado to assume that Ch0_ca_p/n are not connected to the IP?
03-25-2021 11:32 AM
I also see this warning message during the synthesis. Not sure if it has something to do with the IP itself?
[Synth 8-7071] port 'data_to_fabric_ch0_ca_n' of module 'ip_rx_bank65_high_speed_selectio_wiz_v3_6_0' is unconnected for instance 'inst' ["c:/2Projects/gx5270_top/gx5270_top.srcs/sources_1/ip/ip_rx_bank65/synth/ip_rx_bank65.v":967]
04-19-2021 06:44 AM
You said " these pins are connected to the ip_rx_bank66_inst." however in the screen grab you it is ip_rx_bank65_inst. The error message is also for ip_rx_bank65. Was the bank66 a typo?
I would suggest your next step is to open the Example Design (right click on your XCI and select Open IP Example Design), you should be able to implement the Example design and validate the the XCI is setup correctly.
Assuming it is then you can check on the differences between how the Example Design hooks up the XCI at the toplevel and how it is done in your design.
In the Wizard when you have a Differential input pair by default the Wizard will output both P and N side, so you get a copy of the deserialized data. It can be useful if you are you a Dynamic Phase Alignment (like the Aysnch mode uses). If you do not need it or use then you can deselect the option on the Advanced Tab of the Wizard and that should resolve the specific Synth message above that data_to_fabric_ch0_ca_n is unconnected.