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rwnbiad
Newbie
Newbie
6,108 Views
Registered: ‎04-02-2016

Vivado Placement Error [Place 30-681]

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I have a problems for PnR with vivado

I made a clock with MMCM, and MMCM Input is a clock (Global clock capable IO pin)

I just connect top module input clock to MMCM input port.

How can I solve the problem?

===================================================

ERROR: [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
        clk_gen_50M/inst/clkin1_ibuf/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y23 (in SLR 0)
        clk_gen_50M/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y2 (in SLR 0)

        The above error could possibly be related to other connected instances. Following is a list of
        all the related clock rules and their respective instances.

        Clock Rule: rule_bufgce_bufg_conflict
        Status: PASS
        Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
        used at the same time
        clk_gen_50M/inst/clkf_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y71 (in SLR 0)

        Clock Rule: rule_mmcm_bufg
        Status: PASS
        Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
        BUFG
        clk_gen_50M/inst/mmcme3_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y2 (in SLR 0)
        clk_gen_50M/inst/clkf_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y71 (in SLR 0)

        Clock Rule: rule_bufgce_bufg_conflict
        Status: PASS
        Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
        used at the same time
        clk_gen_50M/inst/clkout1_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y70 (in SLR 0)

        Clock Rule: rule_bufgce_bufg_conflict
        Status: PASS
        Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
        used at the same time
        clk_gen_50M/inst/clkout2_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y69 (in SLR 0)

Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The MMCM is placed in the same clock region as the GCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. For a workaround, please insert a BUFG on the GCIO-MMCM path.

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pratham
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Registered: ‎06-05-2013

@rwnbiad I have not read complete message but i believe resolution message is very clear, please insert a BUFG between GCIO and MMCM.

-Pratham

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pratham
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10,678 Views
Registered: ‎06-05-2013

@rwnbiad I have not read complete message but i believe resolution message is very clear, please insert a BUFG between GCIO and MMCM.

-Pratham

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vemulad
Xilinx Employee
Xilinx Employee
6,021 Views
Registered: ‎09-20-2012

Hi @rwnbiad

 

Please post the complete FPGA device name.

 

Which package pin are you using for clock input? 

Thanks,
Deepika.
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rwnbiad
Newbie
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5,987 Views
Registered: ‎04-02-2016

I used XCVU440-FLGA2892

Pin Numver - BM45 (IO_L13P_T2L_N0_GC_QBC_39) : Single Ennded

 

Thanks

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vemulad
Xilinx Employee
Xilinx Employee
5,975 Views
Registered: ‎09-20-2012

Hi @rwnbiad

 

As per the error the clock port is located at IOB_X0Y23 which is BL43 package pin.

 

Do you have multiple clock ports locked to clock region X0Y0 (IO bank 39) and they are driving multiple MMCM instances? There is only MMCM site per clock region.

 

You can try locking the instance mentioned in the error message to MMCM site in clock region X0Y0 using constraint below

 

set_property LOC MMCME3_ADV_X0Y0 [get_cells clk_gen_50M/inst/mmcme3_adv_inst]

Thanks,
Deepika.
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