Why Zynq Ultrascale PS in Block Diagram has only 95 bits of EMIO?

[gouthamp]

Hi,
 
I just enabled EMIO pins of Zynq ultrascale+ for my application. I was expecting it to have 96 bits ( 3 banks of 32 bits each), according to Zynq ultrascale+ architecture. But Why does block diagram shows only 95 bits of EMIO . I can see [0:94] and not [0:95]. Why is this? Ideally it must have 96 bits isnt?
 
  I am using Ultrazed of Avent and their board file in Vivado 2016.4 .
Goutham

[gouthamp]

Sorry I meant Ultrascale+.

[htsvn]

hi,

would that be possible to attach the project here?

--hs

[gouthamp]

I am afraid I wont be able to attach project  file here as it as a company project . But basically if you open the zynq ultrascale+ IP in block diagram of vivado , and click on GPIO, and then EMIO, u can see the bits only from [94:0] and not from [95:0].

Environment: Ultrazed board from Avnet, its board file definitions used. (both in 2016.2 and 2016.4)

Thanks

Goutham

[htsvn · Accepted solution]

hi,

the reason you are seeing [94:0] in the GPIO EMIO is because there is a Fabric Reset Enable option likely set to "1" which will be routed using GPIO routed via EMIO. If you disable the Fabric Reset Enable check mark, then you should be seeing [95:0]

attached is the snapshot

--hs