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faberr
Visitor
Visitor
8,257 Views
Registered: ‎04-07-2015

Why does KU060 Ultrascale LUT Utilization increase when false_path constraints are added???

Xilinx Helpdesk,

 

Initially, I had a design which did not meet timing in Kintex XC7K325 device and my place/route LUT utilization was 82%.

After I added false-path constraints to my project, the design met timing and my overall place/route LUT utilization was still about 82%. The place/route LUT utilization did not increase when I added my false-paths.

 

I then created a new design, which had 4 instantiations of my initial design above, and ported my new design to an Ultrascale  KU060 device. If I don't use any timing constraints, my place/route LUT utilization is 67.83% and the new design does not meet timing. When I created and added false-path constraints to my project, my place/route LUT utilization increased to 83.27%.

 

Although my timing is much better, do you know why my P/R LUT utilization increased by 25% in the ultrascale device?

 

Thanks,

Roy

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5 Replies
faberr
Visitor
Visitor
8,254 Views
Registered: ‎04-07-2015

I meant to say 16% increase not 25%.
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eric_delage
Explorer
Explorer
8,247 Views
Registered: ‎10-01-2014

Difficult to say with optimisation algorithm given that the initial conditions changed. However it may be because it gave up initially and rapidly when it thought that it will not be able to reach your timing constraints while, with the false paths, it was able to satisfy the constraint and timing optimization are often by nature hugh consumer of gates (because of signal replication and so on).

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vemulad
Xilinx Employee
Xilinx Employee
8,243 Views
Registered: ‎09-20-2012

Hi @faberr

 

You can generate and compare the hierarchical utilization reports to identify to which module these extra cells belong to.

Thanks,
Deepika.
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faberr
Visitor
Visitor
8,225 Views
Registered: ‎04-07-2015

Are you saying the LUT utilization increase may only be the result of the P/R tool behaving as expected,

and not due to architectural differences between the Kintex-7 vs Kintex-Ultrascale devices that will cause

the LUT utilization to always increase when the P/R tool starts to achieve timing closure in an Ultrascale device?

 

I just want to make sure that the LUT utilization increase is not an expected characteristic specfic to Ultrascale devices.

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faberr
Visitor
Visitor
7,823 Views
Registered: ‎04-07-2015

I also noticed that by adding false_path constraints during synthesis, my synthesized LUT utilization also increased from

(78.26% without any false path constraints) to (92.44% with false_path constraints). So, the P/R LUT utilization seems to follow

the synthesis LUT utilization (67.83% without any false path constraints) and (83.27% with false path constraints).

 

Does it make sense that my false path contraints also affect my synthesis LUT utilizations?

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