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Explorer
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Registered: ‎08-15-2014

Will ODDR/OSERDESE3 be affected by DDR3 mig

hi, I met a very trikcy problem.

I am using ODDRE1/OSERDESE3(Tried both) to send data. it could work in one design, but it failed on another design.

Debugging more, I found if I disable the DDR3 module(MIG) in the problem design. it will work well also.

I don't understand why ODDR3E1/OSERDESE3 would be affected by MIG?

1. the OSERDESE3/ODDRE1 use a GLK0 from board for the MMCM which generate the fastclk, divclk was got by a BUFGCE_DIV .

2. the MIG clk is using a different GCLK1 on board.

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