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Observer
Observer
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Registered: ‎07-02-2018

ZCU102 PL DDR 4GB Map DMA

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Hi,I need a hint. I am trying to use the Build-in PL 4GB DDR4 Module on the ZCU102.

I have included the MIG into the design and I am able to transfer and read some memory regions.  I got 2 DMAs. One from Zynq to PL DDR and the other from PL DDR to Zynq. My test consists of writing the whole 4GB memory with pseudorandom sequence and then reading it back in chunks of 32MB. I have checked the Length of the DMA and the drivers and I belive they are 100% alright. Now if I try this test, the last 512MB portion of the memory reads successfully, the other 3.5GB fails without even a single valid word. If I do the same test during init with the first 32MB range,it writes and reads successfully as well. Perhaps there is some misunderstanding with the mapping of the MIG?

IE why there are only 29 bits if I try to access 4GB of memory,which requires 32 bits?

The DDR is mapped from 0x0 to 4GB with offset 0x00. I have included unaligned mapping,but as I say I do the transfers in 32MB. The AXI burst is 64 beats and connected to Cache Coherency ports,so the problem is definitely not in cache.

I have ILA checked the A_AXI Addr,which is 128-bits. Each burst (64 x Data = 64x128/8B = 1024B),the addr is incremented by  0x400,which seems to be correct.

I have read in the MIG,that 3 LSBs are used for column mapping or whatever. This would solve the issue with the missing bits,but If I try to just discard the lower 3 bits,it doesnt work either.  

I have also double checked the pinout of the DDR and cannot find any bug even there. Any help appreciated. Thanks in advance.

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Observer
Observer
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Registered: ‎07-02-2018

Ok,thank you all for

#1 Great support.

#2 Great documentation.

Consider this topic closed.

PS for xilinx: Never in my life have I seen MEMORY CAPACITY specified in bits rather than bytes (Maybe except for D-Flip Flop). Surely 4G reads better for marketing purposes. I would however rather see an update for the ZCU102 documentation with both capacity in Bytes and bits, as this is confusing.

 

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Observer
Observer
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Registered: ‎07-02-2018

I found out,that 0-512MB tests are OK as well as all other memory test ranges if the total testing area is 512MB. If I run the test from 0x00 to 1GB,then as expected the last 512MB portion is alright while the first 512MB fails. This must be caused by a wrong configuration of the Address map/AXI interconnect I believe. But then again, how do I Map whole 4GB region to 29 address bits? Or whats the magic behind the mapping?

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Observer
Observer
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Registered: ‎07-02-2018

Ok,thank you all for

#1 Great support.

#2 Great documentation.

Consider this topic closed.

PS for xilinx: Never in my life have I seen MEMORY CAPACITY specified in bits rather than bytes (Maybe except for D-Flip Flop). Surely 4G reads better for marketing purposes. I would however rather see an update for the ZCU102 documentation with both capacity in Bytes and bits, as this is confusing.

 

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