11-11-2020 11:20 AM
I'm using a ZCU102 to control a few different boards, and I'm wondering about the PMOD pin state on powerup.
According to this page, I would expect the pins to be tri-state on boot, but that's not the behavior that I'm seeing. I've verified that R397 is installed and R291 is not, so PUDC_B should be pulled high. Here's an example of the behavior I'm seeing. The traces represent 6 of the PMOD pins on J55.
Thanks for any help or suggestions you can provide.
11-11-2020 04:55 PM
Pins of J55 are connected to the PL bank-47 which is an HD bank. With PUDC_B pulled-up via R397 on the ZCU102 board, you are correct that pins of J55 should be tri-stated during FPGA configuration.
So, with a tri-stated pin, it is up to you to determine its state - using either a pullup or a pulldown resistor.
If you place a 1K pulldown resistor on the pins of J55, does this change the oscope traces you have shown?
11-12-2020 06:14 AM
Thanks for the reply.
I should have mentioned in my post, I have 10kΩ pulldowns on my board, so it should be pulled down already. 1kΩ seems like quite a stiff pulldown, is that really necessary?
11-12-2020 03:57 PM
Yes, 1K is a stiff pulldown. However, your 10K pulldowns should have held those tri-stated I/Os low during FPGA configuration.
Another thing that can cause problems with tri-stated I/Os during powerup is not observing the recommended powerup sequence for voltages of the FPGA (see page 16 of data sheet, DS925(v1.18), for FPGA on ZCU102). I suspect the ZCU102 board is following the recommended sequence, but you might want to use an oscope to verify this.
11-13-2020 07:37 AM
I'm checking with my HDL guys to see what the power sequence is. Thanks for pointing that out.
We did some experiments to determine when the pins go HIGH, and it looks like it's happening in the FSBL.