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ksram1988
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Registered: ‎07-16-2019

ZCU111 Loopback - ILA Idle

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Hi

I am trying the following design on ZCU111. The design is a replica of Xilinx training experiment which involves a loopback. I did everything according to the procedure. Generated Bitstream. Configured the clocks through SCGUI. But no matter how many times I do,

1) I get system ILA Idle. 

2) I don't see the adc and dac waveform signals in the ILA window.

What could be going wrong? Please help.

dcimp1.PNGdcimp2.PNGdcimp3.PNGdcimp4.PNGdcimp5.PNGdcimp6.PNGdcimp7.PNGdcimp8.PNGdcimp9.PNG

 

 

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paulnorris
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Registered: ‎07-17-2020

Hi,
The first thing I would look at is your clocks. If you have an AXI memory mapped master such as the RFSoC's processor then you can use that to interrogate the registers to see if the converter tile's POR state machines have completed, my guess is they're still waiting for a clock in the valid range this is because you've set the sample clock for both the DAC and ADC to be 1.47456 GHz with the PLLs not enabled. However, the ZCU111 Board user interface screenshots you've provided sets the analogue clocks to 122.88 MHz. The only way to configure the clocks is by using the processor in the RFSoC but your design doesn't show the processor or anything connected to the converter tile's AXI bus.

You could try a simple test bench setup with just your instance of the converter tile, provide it with the analogue clocks and write some procedures to perform AXI LITE writes and reads. From my limited experience, in the test bench, you need to start the POR state machine (this would happen automatically when implemented on the hardware IIRC) and then you can poll the registers to see when it completes. The DACs will complete their POR state machine within a few hundred us (simulation time) while the ADCs take maybe as much as twice as long, maybe a bit more. You should see that the tile outputs a clk_dac1 and clk_adc0 once it has completed the clocking part of the POR state machine (there's 15 states in total and state 6 is the start of the clocking portion).

Hope this helps.

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paulnorris
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Registered: ‎07-17-2020

Hi,
The first thing I would look at is your clocks. If you have an AXI memory mapped master such as the RFSoC's processor then you can use that to interrogate the registers to see if the converter tile's POR state machines have completed, my guess is they're still waiting for a clock in the valid range this is because you've set the sample clock for both the DAC and ADC to be 1.47456 GHz with the PLLs not enabled. However, the ZCU111 Board user interface screenshots you've provided sets the analogue clocks to 122.88 MHz. The only way to configure the clocks is by using the processor in the RFSoC but your design doesn't show the processor or anything connected to the converter tile's AXI bus.

You could try a simple test bench setup with just your instance of the converter tile, provide it with the analogue clocks and write some procedures to perform AXI LITE writes and reads. From my limited experience, in the test bench, you need to start the POR state machine (this would happen automatically when implemented on the hardware IIRC) and then you can poll the registers to see when it completes. The DACs will complete their POR state machine within a few hundred us (simulation time) while the ADCs take maybe as much as twice as long, maybe a bit more. You should see that the tile outputs a clk_dac1 and clk_adc0 once it has completed the clocking part of the POR state machine (there's 15 states in total and state 6 is the start of the clocking portion).

Hope this helps.

View solution in original post

dpaul24
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Registered: ‎08-07-2014

@ksram1988 ,

Are you triggering the ILA properly?

You should set some condition which if occurs will enable ILA to log the data and display them.

Please read the ILA docu : https://www.xilinx.com/support/documentation/ip_documentation/ila/v6_2/pg172-ila.pdf  in order to use it successfully.

If you are triggering it, then it might also happen that the trigger condition is not occurring in your design. You should look in to it then, if you have set the trigger already.

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klumsde
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Registered: ‎04-18-2011

Hi @ksram1988 

I'd echo the step suggested by @paulnorris above. The first thing to check is if the Tiles used have completed the start up state machines. 

Second of all I didn't think it was allowed to have one AXI-Stream master driving 2 slaves in this way. I would look at adding the AXIS Broadcaster IP here to connect the DAC source to the ILA and the Tile input 

 

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