10-14-2019 10:57 AM
I got access to the s parameters of the RFSOC. I have a couple of questions on the naming convention used to understand the file contents a little better.
For example, if I open the file ADC_FFVG1517_package.s32p file it has the following designations for the ports
! Port = D1.929.ADC_VIN_I23_N_227
! Port = D1.930.ADC_VIN_I23_P_227
! Port = D1.927.ADC_VIN_I01_N_227
! Port = D1.928.ADC_VIN_I01_P_227
! Port = D1.921.ADC_VIN_I23_N_226
! Port = D1.922.ADC_VIN_I23_P_226
! Port = D1.919.ADC_VIN_I01_N_226
! Port = D1.920.ADC_VIN_I01_P_226
! Port = D1.913.ADC_VIN_I23_N_225
! Port = D1.914.ADC_VIN_I23_P_225
! Port = D1.911.ADC_VIN_I01_N_225
! Port = D1.912.ADC_VIN_I01_P_225
! Port = D1.905.ADC_VIN_I23_N_224
! Port = D1.906.ADC_VIN_I23_P_224
! Port = D1.903.ADC_VIN_I01_N_224
! Port = D1.904.ADC_VIN_I01_P_224
! Port = B1.Y1.ADC_VIN_I23_N_227
! Port = B1.Y2.ADC_VIN_I23_P_227
! Port = B1.AB1.ADC_VIN_I01_N_227
! Port = B1.AB2.ADC_VIN_I01_P_227
! Port = B1.AD1.ADC_VIN_I23_N_226
! Port = B1.AD2.ADC_VIN_I23_P_226
! Port = B1.AF1.ADC_VIN_I01_N_226
! Port = B1.AF2.ADC_VIN_I01_P_226
! Port = B1.AH1.ADC_VIN_I23_N_225
! Port = B1.AH2.ADC_VIN_I23_P_225
! Port = B1.AK1.ADC_VIN_I01_N_225
! Port = B1.AK2.ADC_VIN_I01_P_225
! Port = B1.AM1.ADC_VIN_I23_N_224
! Port = B1.AM2.ADC_VIN_I23_P_224
! Port = B1.AP1.ADC_VIN_I01_N_224
! Port = B1.AP2.ADC_VIN_I01_P_224
I am trying to understand what is the input/output ports in here. Could you please give some clarity on this?
10-21-2019 02:14 PM
What does it say in the readme that comes with these models?
10-21-2019 04:36 PM
The readme file only mentions a very small description of what the file is, but does not mention what the ports are or anything else. (Copied below)
|ADC_On_Die_Correlated_Model.s2p||Hardware correlated ADC on-die model|
|DAC_On_Die_Correlated_Model.s2p||Hardware correlated DAC on-die model|
|ADC_FFVE1156_Package.s48p||FFVE1156 package model-ADC & ref clock channels for ZU25DR/ZU27DR/ZU28DR|
|DAC_FFVE1156_Package.s44p||FFVE1156 package model-DAC & ref clock channels for ZU25DR/ZU27DR/ZU28DR|
|ADC_FFVG1517_Package.s32p||FFVG1517 package model-ADC channels for ZU25DR/ZU27DR/ZU28DR|
|ADC_clk_FFVG1517_Package.s16p||FFVG1517 package model-ADC ref clock channels for ZU25DR/ZU27DR/ZU28DR|
|DAC_FFVG1517_Package.s32p||FFVG1517 package model-DAC channels for ZU25DR/ZU27DR/ZU28DR|
|DAC_clk_FFVG1517_Package.s8p||FFVG1517 package model-DAC ref clock channels for ZU25DR/ZU27DR/ZU28DR|
|ADC_full_FFVF1760_Package.s80p||FFVF1760 package model-ADC & ref clock channels for ZU29DR|
|DAC_FFVF1760_Package.s64p||FFVF1760 package model-DAC channels for ZU29DR|
|DAC_clk_FFVF1760_Package.s16p||FFVF1760 package model-DAC ref clock channels for ZU29DR|
|Reference_CLK_Die.s2p||ADC and DAC reference clock die model|
10-21-2019 06:44 PM
S32 is the package s parameter file of adc input channel.
There are two ports for each channel. One for die and the other for ball.
Port = D1.929.ADC_VIN_I23_N_227 means port of ADC23 on tile 227 N port on die
Port = B1.Y1.ADC_VIN_I23_N_227 means the same channel but on ball. The package pin should be located on Y1
11-04-2019 03:37 PM
Thanks for the reply @zhendon
Pardon my lack of understanding in the matter, could you please elaborate on what that actually means?
As in what does the transmission coefficient between the ball and the die actually correspond to i.e the s171 ? I am essentially trying to understand what the net input frequency response of each ADC channel is and the actual roll-off beyond 4GHz at the ADC input. What would be a good source for me to get hold of this information?
11-06-2019 12:21 AM
We have input bandwidth tested and the input frequency is sweeped from 550Mhz to 6Ghz. The test results can be found in the Char report.
You can find the information in the section " Analog Input Bandwidth Tests "
Hope this can help.
11-27-2019 05:25 AM
I am looking for S-Parameter files and characterisation report mentioned in PG269 RF Data Converter.
I need the S-Parameter files to design the matching network between the Balun and ADC. I'll be using a RF simulator such as ADS or Microwave Office to simulate the matching network.
Are the S-Parameter file for each ADC port, P and N? If you have the simulation file, that would be appreciated.
11-27-2019 05:30 AM
you can find the model.
The package model are including all the ADC/DAC channels.
11-27-2019 05:44 AM
09-11-2020 07:40 AM
09-13-2020 07:07 PM
S- parameter here is only for SI simulation. It can help you achieve impedance matching along the trace to ADC input or DAC output. So it doesn't include anything inside ADC or DAC.
Die correlated model is the model for die and 32p model is the model indicates the package which generally means the ball to die.
09-14-2020 01:06 AM
Hello @zhendon ,
Thanks for the answer. So these parameters cannot be useful in Modeling simulation ? (i.e. Simulink) ( Forgive me for my questions,i am not familiar with this field...) . Is there any way to simulate RFDC IP chain i.e. with Simulink?
09-14-2020 01:34 AM
No worries. ：）
I get your point. It seems that you are asking for a Matlab model of DDC and DUC in ADC and DAC. But I am afraid that these models are not available to the public...
09-14-2020 02:38 AM
Hello @zhendon ,
Thanks for quick answering,
Maybe DUC and DDC can be implemented with PG269 help. But are there any specs for mixer and NCO in some manual so that i can model them?
Also, do Die correlated mode or 32p model S-parameter include XM500 balun network behavior or just before the baluns (and pi attenuator? if i am not wrong) ?
Thanks again ,
09-14-2020 07:50 PM
Sorry I am not very familiar with building models. Would you please let me know what information is needed for modeling NCO and mixer? I may help if the information is available.
ie correlated mode or 32p model S-parameter don't include anything outside FPGA package. So XM500 board s-parameter is not included.
09-16-2020 03:37 AM - edited 09-16-2020 03:45 AM
Hello @zhendon ,
Thanks for helping. About modeling NCO of IQ digital mixer , are there any parameter configurations ? (Accumulator bits, SFDR ,Frequency resolution). Additionally, is there any manual describing the blocks in the picture below?
Crossbar and Coarse delay are trivial. But what about the Output Filter? is it the sinc-inverse filter? Also, is the any possibility having Ideal DAC output Response in some-kind of data format?
Thanks for helping,
Best Regards ,