08-06-2020 04:01 PM - edited 08-06-2020 04:15 PM
I wish to input a single ended clock signal via the SMA MGT P connector (J14) of the ZCU111 board. I added pin T31 as an 'LVDS' IOSTANDARD in my constraints file and then instantiated an IBUFDS_GTE4 followed by a BUFG_GT as suggested in https://forums.xilinx.com/t5/Serial-Transceivers/Zynq-Ultrascale-SMA-MGT-Clock-input/td-p/855914 however I am not able to see the output clock (mapped to header J48.1) on an oscilloscope. I even tried providing a differential clock (180 degrees out of phase) input but do not see any output.
Here are my instantiations:
I use the signal frame_sync_en_outp2 for the rest of my logic. Is there any thing I am missing?
08-10-2020 09:49 PM
IBUFDS_GTE4 is differntial to single ended input buffer for GTs , you need to have differential input (P and N) connected to I and IB inputs and location and IOstandard
constraints in the XDC file.
Here you are only using the P side and constraints for N side are missing.
to check the output clock , you need forward it in recommended way
i.e BUFG_GT -> ODDR -> mapped to any GPIO.
ODDR will ensure that your clock stays on clock dedicated network.
Connected the clockout from BUFG_GT to CLK input of ODDR and tie D1=''1 and D2 = "0".