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Visitor
Visitor
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Registered: ‎02-03-2020

ZCU111: SMA MGT Clock input

Hi,

I wish to input a single ended clock signal via the SMA MGT P connector (J14) of the ZCU111 board. I added pin T31 as an 'LVDS' IOSTANDARD in my constraints file and then instantiated an IBUFDS_GTE4 followed by a BUFG_GT as suggested in https://forums.xilinx.com/t5/Serial-Transceivers/Zynq-Ultrascale-SMA-MGT-Clock-input/td-p/855914 however I am not able to see the output clock (mapped to header J48.1) on an oscilloscope. I even tried providing a differential clock (180 degrees out of phase) input but do not see any output.

Here are my instantiations:

   IBUFDS_GTE4 #(
      .REFCLK_EN_TX_PATH(1'b0),   // Refer to Transceiver User Guide
      .REFCLK_HROW_CK_SEL(2'b00), // Refer to Transceiver User Guide
      .REFCLK_ICNTL_RX(2'b00)     // Refer to Transceiver User Guide
   )
   SMA_fr_sync (
      .O(),         // 1-bit output: Refer to Transceiver User Guide
      .ODIV2(frame_sync_en_outp), // 1-bit output: Refer to Transceiver User Guide
      .CEB(1'b0),     // 1-bit input: Setting this high powers down the clock buffer
      .I(frame_sync_en_p),         // 1-bit input: Refer to Transceiver User Guide
      .IB(frame_sync_en_n)        // 1-bit input: Refer to Transceiver User Guide
   );
   
   // Adding this to use SMA connector input
      BUFG_GT BUFG_SMA_fr_sync2 (
      .O(frame_sync_en_outp2),             // 1-bit output: Buffer
      .CE(1'b1),           // 1-bit input: Buffer enable
      .CEMASK(1'b1),   // 1-bit input: CE Mask
      .CLR(1'b0),         // 1-bit input: Asynchronous clear
      .CLRMASK(1'b1), // 1-bit input: CLR Mask
      .DIV(3'b000),         // 3-bit input: Dynamic divide Value
      .I(frame_sync_en_outp)              // 1-bit input: Buffer
   );

 

I use the signal frame_sync_en_outp2 for the rest of my logic. Is there any thing I am missing?

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Moderator
Moderator
134 Views
Registered: ‎08-08-2017

Hi @siddadd   

IBUFDS_GTE4 is differntial to single ended input buffer for GTs , you need to have differential input (P and N) connected to I and IB inputs and location and IOstandard 

constraints in the XDC file.

Here you are only using the P side and constraints for N side are missing.

to check the output clock  , you need forward it in recommended way

i.e  BUFG_GT  -> ODDR  -> mapped to any GPIO.

ODDR will ensure that your clock stays on clock dedicated network.

Connected the clockout from BUFG_GT to CLK input of ODDR and tie D1=''1 and D2 = "0".

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