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628 Views
Registered: ‎06-21-2017

Zynq Decoupling

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We are designing a board with a Zynq Ultrascale+ and I have a few decoupling questions.  I'm looking at UG583, the Ultrascale PCB Design Guide, Table 1-6 and I see a recommendation for Vccaux/Vccaux_io for two 47uF caps and three 4.7uF caps.  Just to be clear, is that 5 caps for the combined Vccaux/Vccaux_io rail, or is it 5 caps for Vccaux and five for Vccaux_io?

 

We are not using the Vcc_psbatt and have it connected to the 1.8V Vcc_psaux rail.  Is there any reason to add additional capacitors on top of the recommended caps for Vcc_psaux?

 

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Explorer
Explorer
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Registered: ‎05-08-2018

Re: Zynq Decoupling

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5 for the combined, not 5 each,

 

No, unnecessary to add decoupling to the combined if the power domain is unused.  This domain I believe is used for the built in real time clock (and RAM for keys),

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Explorer
Explorer
741 Views
Registered: ‎05-08-2018

Re: Zynq Decoupling

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5 for the combined, not 5 each,

 

No, unnecessary to add decoupling to the combined if the power domain is unused.  This domain I believe is used for the built in real time clock (and RAM for keys),

View solution in original post