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Visitor nickb123
Visitor
635 Views
Registered: ‎06-27-2016

Zynq US+ DDR4 controller trace delays in SFVC784 package

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Hi,

I'm designing a board which can ideally be assembled with the xczu2eg-sfvc784 device up to the xczu5eg-sfvc784-1LV depending on the application.
When comparing the trace delays between the devices the xczu2eg-sfvc784 and xczu3eg-sfvc784 have the same delays and the xczu4eg-sfvc784 and xczu5eg-sfvc784 have the same delays but they differ between these pairs.

I combined all the trace delays in a spreadsheet and calculated the additional delay that is needed on the pcb for all the groups of signals for both device pairs.
Then I took the mean of the pcb delays and calculated the difference with the ideal delays for both device pairs and compared this to ±8ps tolerance for the data group (32-bit on our board) and ±10ps for the address group.

All the signals seem to be within tolerance except for PS_DDR_ALERT_N_504 and PS_DDR_CKE1_504.
PS_DDR_CKE1_504 is not used in our design (32-bit 1 rank) so the only problem is PS_DDR_ALERT_N_504.
The delay is ±8.5ns, is this still acceptable?
Are there others solutions? Can a certain delay be added to signals using the DDR4 controller?

The spreadsheed is attached to this post.

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Xilinx Employee
Xilinx Employee
602 Views
Registered: ‎03-14-2016

Re: Zynq US+ DDR4 controller trace delays in SFVC784 package

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Hello,

There is no issue with the PS_DDR_ALERT_N_504 signal having a larger tolerance.  In your spreadsheet it is ±9.64ps.  In UG583 v1.13, Table 2-9, the Alert_n signal is classified in the "Other Signals".  It does not have a match requirement.  We do show an example of how the Alert_n signal should be connected on p.69 of UG583.  The alert_n signal is driven by the DRAM back to the FPGA, it is not a synchronous signal. 

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Xilinx Employee
Xilinx Employee
603 Views
Registered: ‎03-14-2016

Re: Zynq US+ DDR4 controller trace delays in SFVC784 package

Jump to solution

Hello,

There is no issue with the PS_DDR_ALERT_N_504 signal having a larger tolerance.  In your spreadsheet it is ±9.64ps.  In UG583 v1.13, Table 2-9, the Alert_n signal is classified in the "Other Signals".  It does not have a match requirement.  We do show an example of how the Alert_n signal should be connected on p.69 of UG583.  The alert_n signal is driven by the DRAM back to the FPGA, it is not a synchronous signal.