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jyb-xiphos
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Registered: ‎10-28-2019

Zynq US+ RFSoC analog Sysref phase requirement

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Hi,

I am currently reading PG269 V2_4 section "SYSREF Signal Requirements" and cannot find the following explicitly (when considering an MTS design):

Is there a phase requirement between the analog sysref and the dac_clk (or adc_clk)?

By dac_clk or adc_clk I mean the ADC or DAC analog clock. There is a clear mention that the PL sysref and the analog sysref must be in phase. It is also mentioned that the sysref must be an integer submultiple of the sampling rate. I would assume that the sysref clocks and the dac_clk or adc_clk must come from the same source (as it is done on the ZCU111 with the LMK04208), but is it possible to source the dac_clk and adc_clk from a different source than all the sysref clocks and PL clock AND still achieve MTS?

Thank you in advance for your help,

JY

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pthakare
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Registered: ‎08-08-2017

Hi @jyb-xiphos 

Yes it is possible. But I wanted to concentrate here on PL refclk.  I presume you will use this as AXI4 stream clock as well , right?

In this case you need to ensure that Stream clocks clock be frequency-locked to the RF-ADC/DAC sample clocks

pthakare_0-1616993502366.png

 

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pthakare
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Registered: ‎08-08-2017

Hi @jyb-xiphos 

There is no phase requirement between Analog Sysref to ADC/DAC sampling clock or ADC/DAC reference clock(Clock for internal PLL) .

The SYSREF section in PCB user guide (page 175) has detailed information on PCB guidelines for SYSREF

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

 

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jyb-xiphos
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Registered: ‎10-28-2019

Hi pthakare,

Thank you for your quick and clear answer. Would you care to comment about this:

Is it possible to source the dac_clk and adc_clk from a different source than all the sysref clocks and PL clock AND still achieve MTS? For instance, on the ZCU111, using the LMK04208 to source the PL refclk, analog sysref and PL sysref AND using SMA connectors to source external DAC_CLK and ADC_CLK to the tiles (respecting all requirements concerning the relation between sysref and DAC/DAC clk frequency).

Regards

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pthakare
Moderator
Moderator
246 Views
Registered: ‎08-08-2017

Hi @jyb-xiphos 

Yes it is possible. But I wanted to concentrate here on PL refclk.  I presume you will use this as AXI4 stream clock as well , right?

In this case you need to ensure that Stream clocks clock be frequency-locked to the RF-ADC/DAC sample clocks

pthakare_0-1616993502366.png

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post