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Visitor majestix69
Visitor
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Registered: ‎09-13-2010

Zynq UltraScale+ Power Sequence Timing & PS_POR_B

Dear all

I've got the following two questions about power sequencing in a Zynq UltraScale+ application:

  • Where can the timing requirements (if any exist) of the power sequence be found (e.g. how long to wait after stable VCCINT until power-up of VCCAUX)? Neither of UG583 nor DS925 elaborate on this.

  • DS925 states "The FPD (when used) must be powered before PS_POR_B is released". What, if I want to bring up LPD first and subsequently with active LPD bring up FPD as well (only as long as APU required)? If I need to assert PS_POR_B bringing up FPD, I assume this will reset the already running LPD as well. How to handle this?

Best regards,
Peter

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Explorer
Explorer
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Registered: ‎03-17-2011

Re: Zynq UltraScale+ Power Sequence Timing & PS_POR_B

I can only answer to the first point. I believe there is no timing specified. just the sequence and the ramp-up.

As an example, in our case, we used a 10ms delay between power-ups

--Sebastien
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