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bruce_karaffa
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Registered: ‎06-21-2017

Zynq UltraScale+ Power Supply Sequencing

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We are designing a board with a ZCU9EG.  We were planning to use the power supply design from the ZCU102 board as an example, but with 26 pages of power supplies in the schematic, we are hoping that there may be some simplifications.

 

Page 14 of the data sheet (ds925) states; "The low-power domain (LPD) must operate before the full-power domain (FPD) can function. The low-power and full-power domains can be powered simultaneously. The PS_POR_B input must be asserted to GND during the power-on sequence (see Table 37). The FPD (when used) must be powered before PS_POR_B is released."

 

Does this mean that the LPD and FPD can be powered up (sequenced) simultaneously or simply that power may be present on the LPD and FPD at the same time?  I believe the sentence implies the former, not the latter, but the cost and schedule delay of a second board spin would be detrimental to my career.

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austin
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Registered: ‎02-27-2008

The former,

 

You may power both the LPD and HPD from the same supply.  Releasing the PS_POR_B once that supply is at or beyond 90% of its specified value.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
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Registered: ‎02-27-2008

The former,

 

You may power both the LPD and HPD from the same supply.  Releasing the PS_POR_B once that supply is at or beyond 90% of its specified value.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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bruce_karaffa
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Registered: ‎06-21-2017

Austin

 

Thanks, I was pretty sure that's what it meant, especially after I got the Maxim DigitalPower software loaded and saw how the delays were set on the ZCU102.

 

Bruce

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