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Visitor jblank
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Registered: ‎02-06-2019

Zynq UltraScale+ Single-Ended and Differential Connections

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Hello everyone,

I have a question regarding the Zynq UltraScale+. Take this SoM for example: https://shop.trenz-electronic.de/en/TE0808-04-09EG-2IE-UltraSOM-MPSoC-Module-with-Zynq-UltraScale-XCZU9EG-2FFVC900I-4-GB-DDR4

Is it possible to allocate certain pins to being differential or do you have to allocate the entire I/O bank to being differential? Similarily, if I want to use single-ended signals, does the entire I/O bank have to consist of single-ended signals? 

Thank you.

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Registered: ‎06-21-2017

Re: Zynq UltraScale+ Single-Ended and Differential Connections

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You may allocate some pins in a bank to be differential and some to be single ended.  You must select IO standards compatible with the bank type (HP or HR) and with teh VCCO powering that bank.

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Registered: ‎06-21-2017

Re: Zynq UltraScale+ Single-Ended and Differential Connections

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You may allocate some pins in a bank to be differential and some to be single ended.  You must select IO standards compatible with the bank type (HP or HR) and with teh VCCO powering that bank.