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aggelos
Observer
Observer
11,811 Views
Registered: ‎12-04-2015

Zynq UltraScale+ (ZU9EG) Clock Pins usage from neighbouring banks?

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Hello,

 

We are building a design for the ZU9EG (xczu9eg-ffvb1156-2-i-EVAL). We include modules for fast fpga-to-fpga communication through LVDS pairs. For this we have to use the HP banks. Our data inputs/outputs consume exactly all the pins of the 2 HP banks. What remains to be inserted are 3 clock input pins. The other two HP banks pins (almost all) are occupied by the Xilinx DDR4 32-bit wide controller (MIG). And the pins that remain here are not clock-capable pins. Also if we try to use the clock-capable pins of the neighbour HD bank we get an Implementation error: (The Input buffer driving a PLL clock input needs to be in the same clock region as the PLL or driving an appropriate Clock buffer for the PLL clock input…). Could you please provide us with any suggestions?

 

I rephrase the question in fewer words: Can I drive logic in an HP bank, with a clock coming from another (probably HD) bank?

 

(Insight: If for example the DDR4 controller is omitted, I was able to use the clock-capable pins of these HP banks successfully. But we need advice under the circumstances described above)

 

Thank you very much in advance,

And excuse us for the lengthy description,

 

Greetings,

Angelo

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vemulad
Xilinx Employee
Xilinx Employee
21,310 Views
Registered: ‎09-20-2012

Hi @aggelos

 

I understand that you are trying to use GCIO pin in HD bank for clock port.

 

There are no PLL/MMCM sites in HDIO bank hence it is necessary to instantiate BUFG in between IO and PLL. Please try instantiating a BUFG and let me know if that helps.

 

 

 

Thanks,
Deepika.
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trenz-al
Scholar
Scholar
11,793 Views
Registered: ‎11-09-2013

HD bank should be really considered as simple 3V IO extension for EMIO routed peripherals and for some low performance IO.

 

It is possible that Xilinx relaxes the MIG DDR4 requirements someday but to be on the safe side I would suggest to obey the MIG4 requierements for the placement.

 

If you are out of CC pins for MIG clock I see no options as to rething you system level design so that you have the clock pins free.

 

And open an SR.

 

Cant you use the GT ?

Can you increase the bitrate and reduce the number of differentual lanes for the chip to chip connection?

 

but I am surprised, you say it is not possible to:

 

place 32 bit DDR4 + 1 Clock input for DDR clock in 2 banks?

 

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aggelos
Observer
Observer
11,786 Views
Registered: ‎12-04-2015
The two ideas you correctly mentioned (GTs or narrower data pins) are under our consideration.
However this would need great changes.
Also you mention about the DDR (MIG). This is placed normally in two banks.
The problem is that it is impemented in such a way that it occupies all the clock capable pins,
and so no such pins remain for the chip to chip.
As for the SR, you suggest that I should place my question under a SR? This works better? (I am quite
new user of the Xilinx online support services)

 

 



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vemulad
Xilinx Employee
Xilinx Employee
21,311 Views
Registered: ‎09-20-2012

Hi @aggelos

 

I understand that you are trying to use GCIO pin in HD bank for clock port.

 

There are no PLL/MMCM sites in HDIO bank hence it is necessary to instantiate BUFG in between IO and PLL. Please try instantiating a BUFG and let me know if that helps.

 

 

 

Thanks,
Deepika.
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aggelos
Observer
Observer
11,728 Views
Registered: ‎12-04-2015

Hi,

and many thanks @vemulad for the reply! It seems to work correctly this way!

 

Before I mark this as a solution, I would be glad if I can have some more clarifications:

Each HP bank has 2 PLLs and one MMCM, and these are all the clock sources, correct?

Can I use all three for 3 independent in and/or out clocks?

We would had an easier design if we could use 6 clocks (3 in & 3 out) for the logic in the two HP banks (all clock pins have to come from other banks). Is this possible? Can a PLL of a neighbour HP bank drive the logic of another HP bank?

I actually ask this last question, because when I tried to use an MMCM instead of a PLL (in the already working design with the BUFG fix), I got this error:

 

[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair…
… IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y26

clkf_buf__0 (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y17
The above error could possibly be related to other connected instances…

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vemulad
Xilinx Employee
Xilinx Employee
11,721 Views
Registered: ‎09-20-2012

Hi @aggelos

 

Can you attach the post opt_design (_opt.dcp) file?

 

Thanks,

Deepika.

Thanks,
Deepika.
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aggelos
Observer
Observer
11,716 Views
Registered: ‎12-04-2015

Hi @vemulad

is this a file that contains detailed error info?

Is it auto-created, or I have to create it myself?

(I did not keep a copy of the erroneous project state, but I can recreate it)

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vemulad
Xilinx Employee
Xilinx Employee
11,714 Views
Registered: ‎09-20-2012

Hi @aggelos

 

Its automatically generated by Vivado. You can find it in project_name.runs --> impl_1 folder.

 

I can check the partial placement using this file.

Thanks,
Deepika.
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aggelos
Observer
Observer
11,443 Views
Registered: ‎12-04-2015

Hi @vemulad,

 

since I am considering nda/IP issues, is posting such a file ok?

Doesn't it include too much info?

Would it also be a solution to send it to you personally?

 

Thanks

Angelo

 

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vemulad
Xilinx Employee
Xilinx Employee
11,440 Views
Registered: ‎09-20-2012

Hi @aggelos

 

I will send you ezmove package to upload the file. Please check your PM for ezmove login credentials.

 

In case if you need NDA then please open SR from service portal. 

Thanks,
Deepika.
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