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Visitor
Visitor
4,504 Views
Registered: ‎05-21-2014

Zynq Ultrascale+ DDR3 Connections?

Greetings all,

 

My team and I (at work) are currently implementing a design using the ZU15G, Zynq Ultrascale+ device. We have a need to use DDR3 instead of DDR4 for our design. The trouble is, we can't seem to find any piece of literature within the TRM that explains what a few of the DDR3 connections must be if you opt to use it.

We have a board design where we are using three (3) micron memory ICs connected directly to the PS side of the chip. We are using two (2) chips to form a 32-bit data bus and the third chip for ECC using only the lower 8-bits of the device. The problem is, that the connections from the packaging info doesn't seem to include pins that we need to connect. These pins are the following:

 

- Bank Address 0, 1, and 2 (only 0 and 1 appear to be available)
- Column Address Strobe connection pin
- Row Address Strobe connection pin

- Upper / Lower Data Masks connection pins

- Upper / Lower DQ Strobe connection pins

- Write Enable connection pin

 

I understand that this device is new, so if anyone can point me to a document or aid us in our venture to ensure our board design properly connects these ICs to the chip, your help would be greatly appreciated. Thank you.

 

-E

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Xilinx Employee
Xilinx Employee
4,469 Views
Registered: ‎08-01-2008

check these documents
http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf
https://forums.xilinx.com/t5/Xcell-Daily-Blog/New-UltraScale-pcb-user-guide-gives-advice-on-connecting-FPGAs/ba-p/551200
http://www.xilinx.com/support/documentation-navigation/design-hubs/dh0061-ultrascale-memory-interface-ddr4-ddr3-hub.html
Thanks and Regards
Balkrishan
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Visitor
Visitor
4,435 Views
Registered: ‎05-21-2014

Those documents do list typical connections for DDR3 / DDR4 for the device. However, we are trying to use the PS-DDR Bank (Bank 504 on the Zynq Ultrascale+ ZU15 device) for said connections.

 

The packaging / pin information for the Ultrascale+ device only shows DDR4 pins connections, and none of the literature indicates where the pins I listed should connect if using DDR3.

 

We're essentially stuck.

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Visitor
Visitor
4,433 Views
Registered: ‎05-21-2014

Nevermind, it looks like the PCB design guide has a supplemental section for it. Thank you.
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3,215 Views
Registered: ‎11-01-2016

Did you ever find a pin to put BA(2) on?
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Moderator
Moderator
3,200 Views
Registered: ‎07-23-2015

mbell@janteq.com Did you try using the Schematic checklist spreadsheet?

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=423500&license=RefDesLicense&filename=xtp427-ultrascale-plus-schematic-review-checklist.zip&languageID=1

 

Based on the memory you choose, it should show up the respective pin connections 

- Giri
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3,189 Views
Registered: ‎11-01-2016

Great!  Thanks it's in the checklist spreadsheet when you fill out part# etc

 

Many thanks

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