08-07-2016 03:38 PM
My team and I (at work) are currently implementing a design using the ZU15G, Zynq Ultrascale+ device. We have a need to use DDR3 instead of DDR4 for our design. The trouble is, we can't seem to find any piece of literature within the TRM that explains what a few of the DDR3 connections must be if you opt to use it.
We have a board design where we are using three (3) micron memory ICs connected directly to the PS side of the chip. We are using two (2) chips to form a 32-bit data bus and the third chip for ECC using only the lower 8-bits of the device. The problem is, that the connections from the packaging info doesn't seem to include pins that we need to connect. These pins are the following:
- Bank Address 0, 1, and 2 (only 0 and 1 appear to be available)
- Column Address Strobe connection pin
- Row Address Strobe connection pin
- Upper / Lower Data Masks connection pins
- Upper / Lower DQ Strobe connection pins
- Write Enable connection pin
I understand that this device is new, so if anyone can point me to a document or aid us in our venture to ensure our board design properly connects these ICs to the chip, your help would be greatly appreciated. Thank you.
08-07-2016 10:25 PM
08-08-2016 06:45 AM
Those documents do list typical connections for DDR3 / DDR4 for the device. However, we are trying to use the PS-DDR Bank (Bank 504 on the Zynq Ultrascale+ ZU15 device) for said connections.
The packaging / pin information for the Ultrascale+ device only shows DDR4 pins connections, and none of the literature indicates where the pins I listed should connect if using DDR3.
We're essentially stuck.
11-03-2016 10:44 PM
firstname.lastname@example.org Did you try using the Schematic checklist spreadsheet?
Based on the memory you choose, it should show up the respective pin connections