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jt94096
Adventurer
Adventurer
817 Views
Registered: ‎09-21-2018

Zynq Ultrascale+ VCCINT_VCU decoupling

I would like to understand the justification for the VCCINT_VCU decoupling listed as a requirement in DS583 v1.19 Table 1-12.

The table lists three 470uF polymer capacitors in addition to roughly 1000uF of ceramic capacitors. I would prefer not to use the polymer capacitors, mainly due to board space. The polymer caps won't help much with step changes in load and my supply already performs well in this respect with much less ceramic capacitance. Therefore I don't see what benefit the polymer caps would provide.

Thanks - Jason

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3 Replies
simon
Xilinx Employee
Xilinx Employee
745 Views
Registered: ‎08-25-2010

Hi @jt94096 

If you don't follow decoupling capacitors in table 1-12, you should do PI simulation to meet our spec(the performance of the decoupling networks presented here)

Thanks
Simon
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jt94096
Adventurer
Adventurer
737 Views
Registered: ‎09-21-2018

Thanks Simon,

Does Xilinx have PDN sim results for one of their dev boards such as the ZCU106 that can be used for comparison? Or perhaps an impedance spectrum mask? I am not an expert on PDN simulation but I expect that the regulator performance also plays a role at the lower end of the spectrum.

Given the challenges and costs (in time and money) of obtaining accurate post-layout PDN sim data, we also want to have a sound engineering basis for the PDN design. Our regulator supplier has stated that they see no need for this much bulk decoupling and in fact it tends to be detrimental to the performance of the regulator.

Jason

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IAM_NOT_IAM
Visitor
Visitor
322 Views
Registered: ‎04-22-2021

if you have higher DC/DC switch frequency like 2MHz, i think you can reduce the number of 470uF cap

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