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Newbie rajneesh.j
Registered: ‎12-26-2018

Zynq ultrascale+ MPSoC LVDS signalling on HR bank

Hi All,

We are using ZU5EG-1B900 FPGA where we need LVDS  signalling in HR bank at 3.3V bank voltage. The banks available is HR only, as per IO planning.

1.) Which all voltages are supported for LVDS signalling in the HR banks?

2.) If the external driver is driving LVDS at 1.8V, can the HR bank at 2.5V or 3.3 V be able to latch the data?

Thanks and Regards,



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Xilinx Employee
Xilinx Employee
Registered: ‎06-06-2018

Re: Zynq ultrascale+ MPSoC LVDS signalling on HR bank

Hi @rajneesh.j,

1. Only LVDS_25  is supported in HR bank. However, LVDS_25 input can be used in non-2.5V banks with some caveats.

Check this AR: https://www.xilinx.com/support/answers/43989.html.

2. Check the external driver Vodiff and Vocm specs and if they are within range of the Vidiff and Vicm of LVDS_25, you are good and data will latch.



Deepak D N


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