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uts
Visitor
Visitor
362 Views
Registered: ‎04-07-2021

Zynq ultrascale power rail ramp time requirements

Table 11 in ds925 specifies power supply ramp time. Does the 40 ms max mean each rail can take 40 ms to ramp up? Or, does it mean 40 ms max from 1st power rail start to last power rail up?

By referring to the page 10-12 of the DS925, the power supply sequencing order is listed but I haven't found the required timing between these stages. What should be the minimum delay between these voltages?

ds925_cap.PNG
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panantra
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎06-13-2018

Hi @uts ,

Does the 40 ms max mean each rail can take 40 ms to ramp up? Or, does it mean 40 ms max from 1st power rail start to last power rail up? 

--- It means each rail may take min 0.2ms and max 40ms time to ramp from GND to 95% of the Voltage value for that rail.

We do not have any time requirement between power rails. 

Just follow the guidelines given in DS925. Refer table no. 37 as well as Table no. 129 for Tpspor and Tpor requirements.

 

Thanks,

Priyanka

 

 

 

uts
Visitor
Visitor
273 Views
Registered: ‎04-07-2021

Hi @panantra 

Thanks for the information. I am working on a new design with XCZU15EG. I want my power supply to have internal sequencing. Where can I get support?

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gnarahar
Moderator
Moderator
195 Views
Registered: ‎07-23-2015

@uts A general recommendation for power sequence is to power the next power rail after the previous power rail reaches 90% of recommended voltage. 

I want my power supply to have internal sequencing. Where can I get support?

Not sure what you mean by internal sequencing 

- Giri
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barriet
Xilinx Employee
Xilinx Employee
179 Views
Registered: ‎08-13-2007

You may find the reference designs (by device family) useful here as a starting point:

https://www.xilinx.com/products/technology/power.html#partners

Cheers,
bt

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