11-15-2018 01:13 AM
Now i am working on the hardware design for this chip in full power mode refer to below guideline from Xilinx.
I want to know if the figures (from 1 to 14) are the power sequence? if yes, VPS_MGTRAVCC（10）and MGTRAVTT（11）are powered after VCC_PSDDR_PLL（6）and VCCO_PSDDR（7）, right?
but according another description, please see below:
VPS_MGTRAVCC（10） is powered before VCCO_PSDDR（7）which is in conflict with above description.
So which one is correct? which one I should follow?
it is very urgent.
thanks for quick response!
11-15-2018 03:47 AM
I want to know if the figures (from 1 to 14) are the power sequence? if yes, VPS_MGTRAVCC（10）and MGTRAVTT（11）are powered
No, the numbers don't represent power sequencing. Since rails are clubbed together, they just indicate the number of regulators required for each scheme mentioned in UG583 i.e. the 4 Power Supply Consolidation schemes.
If you notice in Table 1-19, it refers to follow Datasheet DS925 for sequencing which is what you need to follow.
11-15-2018 07:21 PM
thanks for your quick respose!
Q1: How to understand below:
Q2: Most of the power solution using PMBUS to control the power sequence. my confusion is that when the chip is not pre-programmed (using default register value or factory setting), the power output is only controlled by the enable pin of the chip, this enable pin has no power sequence in schematic design. this means almost all power rails are powered simultaneously. or the chip must be pre-programmed before it is soldered on the PWB board.
please help to clarify.
11-15-2018 08:59 PM
1. The LPD has the PMU(Platform Management Unit) and hence the reason of LPD operating before FPD. Below is the figure from UG1085 showing the Power Doamins and Islands
2. Generally when you do a mass production of the board, you pre-program the PMBUS power regulators before assembling on the board or program it post assembling on the board. It varies from customer to customer. If you have the Enable pins, you still can control the sequencing by using Power Good output of 1st regulator tied to the Enable pin of the regulator in next sequence. Its a common implementation scheme used.
11-18-2018 06:36 PM
i know what you mean, but my question is: take xilinx Demo board for an example, when i first assembled the chip (it is not pre-programmed), all power rails are powered simultaneous, they don't follow the power sequence requirement.
below is the link of Xilinx Demo board.
11-19-2018 02:32 AM
@wang_3130 The ZCU102 comes with the Maxim Power controller programmed to power the board as per sequence. Do you have a ZCU102 that is not doing the same?
11-21-2018 12:58 AM
ZCU102 is ok, i am just thinking the sch design of XCZU3EG, my solution is as list below:
1: first powered on (there is no pre-programmed chip) , sequence is depending on the enable sequence(hardware control). right? or don't need to control the power enable sequence?
2: Program the Power controller as power sequence.
3: After all, the power sequence is controlled by PMBUS.
11-21-2018 01:07 AM
another question about the PS_POR_B.
In the document DS925, PS_POR_B must be asserted Low at power up and continue to be asserted for a duration 10us after all the PS supply voltages reach minimum levels.
but in ZCU102 sch design, the PS_POR_B is released after VCC_PSAUX is powered. At this time the power of PS-FPD is not powered up. why?
12-05-2018 11:52 PM
For the first time, if you power all the rails at once, it is fine since the datasheet says, the sequencing mentioned is a recommendation to achieve minimum current draw and have I/O's in 3-state. So for the first time, if you power all the rails at once and then program the sequence using PMBUS to sequence from next time, you should be Ok.
Let me check on the ZCU102 schematic you refer to and get back.