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Visitor rocky_dm
Visitor
1,402 Views
Registered: ‎10-25-2018

another question about speed grade

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HI,

 

I m working with Tapped Delay Lines using chains of CARRY8 blocks
with a XCKU040-2FFVA1156E device (speed grade -2).

 

Before buying a new dev board,
I need to know something about the differences, in terms of propagation speed of internal signals, between these two devices:
XCKU040-1FBVA676 and XCKU040-2FFVA1156E.

 

I read from the AC/DC switching characteristics datasheet that the main differences are on the maximum working frequencies of all switching signals.

 

I need to understand particularly if there could be a significant reduction even in the propagation speed
of the carry signals through the carry8 blocks in the XCKU040-1FBVA676 (speed grade -1) device,
respect to the XCKU040-2FFVA1156E (speed grade -2) device.

 

thank you in advance for any kind of help
best regards
Rocky

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Guide avrumw
Guide
1,263 Views
Registered: ‎01-23-2009

Re: another question about speed grade

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as to if one part of a chip can be better than another,

   I doubt , I'd guess all areas are the same wafer,

 

There is definitely some variation on a die - the timing engine even takes this into account. It is by no means as extreme as the variation from wafer to wafer (or more accurately lot to lot), but, nonetheless there is variation.

 

Take a look at this post on how the timing engine deals with on-chip variation.

 

Avrum

 

 

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Adventurer
Adventurer
1,395 Views
Registered: ‎08-30-2018

Re: another question about speed grade

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Hi @rocky_dm,

 

I already have worked with CARRY4 primitive in Virtex-5 FPGA which is the same as CARRRY8 in functionality except the number of carry logics per primitive. I also had these questions in mind at that time that I share them here with you.

 

Speed Grade, is a factor defined by Xilinx to determine the maximum allowed frequency in which the device can operate at the expense of the lowest logic overhead and lowest latency. Let me identify what I mean. Speed Geade can be either -1,  -2, or -3. The larger value, the higher speed and maximum frequency. But, it should be noted that the factor of -2 "DOES NOT" mean the 2x speed higher than -1 neither the -3 factor does not mean 3x higher speed than -1. They are just a factor that indicate a higher speed rate, but Xilinx did not clearly identified how much higher rate they are! Primarily, I thought it is due to intellectual property but later I found that it is not possible to identify how much a -2 speed grade is faster than  -1 cause of the following reasons:

 

  1. Design routability is less controllable. It means that the routing procedure will vary per each implementation unless in some specific cases in Vivado where you manually set a small number of routes(but not all of them, they are thousands of routes!). Hence, the net delay of the paths and critical paths will vary by changing the routing algorithm. It significantly affects the maximum allowed freqenncy and speed.
  2. Locking/Unlocking logic resources while placing and routing is significantly affects the latency, net delay and consequently the speed grade.
  3. Neither two identcal FPGA chips fabricated in the same clean room under the same conditions will not have the same maximum frequency and therefore the same speed grade.

Now, regarding the CARRY8 primitive. Among all types of logic resources inside the FPGA that are highly dependent to the speed grade (r.g., LUT, BRAM, DSP, I/Os, FFs, MUXes, ...) the CARRYx primitives are "less" susceptible to the routing, temperature and latency variations in an impemented design. Please note that choosing an FPGA with higher speed grade will help you to observe lowest latency in data propagation through "x" carry logics of a CARRYx primitive (for your case, "x" equal to 8).

 

Please do not hesitate to ask if you need more explanation.

 

Hope it can help.

Bests,

Daryon

Guide avrumw
Guide
1,387 Views
Registered: ‎01-23-2009

Re: another question about speed grade

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All of what @daryon said is true.

 

But, that being said, the practical advantages of using a higher speed grade is an approximately 10% to 15% speed increase with each speed grade. This is primarily due to the difference in performance of the transistors on the die. Some cells will change more than others, but in general, this tends to be around the right number. 

 

I can make an argument for the CARRY8 being less affected by speedgrade than others since performance in an FPGA is predominantly dictated by the routing delays. The CARRY8 has no routing delay inside the cell, and even the carry path (from one CARRY8 to the one above it) is almost immune to transistor based performance changes (since it is a "pure" propagation delay, as opposed to general routing, where the delay is primarily going through the switching matrices which are cell transistor delays).

 

Avrum

Visitor rocky_dm
Visitor
1,358 Views
Registered: ‎10-25-2018

Re: another question about speed grade

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thank you very much for all your answers


please tell me if I got the right point:
carry8 signals propagation speed, inside the cells and between carry8 blocks, is immune to speed grade changes.
How is it possible to have same Cin->Cout[0-7] delays with a different transistors performance?

 

 

and what about the propagation speed of Cout/Out signals, through the nets and multiplexers between the carry8 block and its FFs, inside a slice? could those internal nets have a different delays in devices with differnet speed grade?

 

thank you again

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Guide avrumw
Guide
1,352 Views
Registered: ‎01-23-2009

Re: another question about speed grade

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How is it possible to have same Cin->Cout[0-7] delays with a different transistors performance?

 

Sorry - I wasn't clear. I was referring solely to the net propagation delay from the COUT of one CARRY8 to the CIN of the one above it. This is a pure transmission line (wire) and hence has very little variability of its delay. The "Carry propagation" calculation within the CARRY8 is definitely transistor based.

 

and what about the propagation speed of Cout/Out signals, through the nets and multiplexers between the carry8 block and its FFs, inside a slice? could those internal nets have a different delays in devices with differnet speed grade?

 

Probably. There are a fair number of MUXes in the slice to control the various inputs to the flip-flops themselves - these will certainly be affected, as will the performance of the flops. 

 

Everything in the device will likely be affected to a certain extent - things like the COUT->CIN route and similar dedicated routes will probably be affected least, but at the same time are already incredibly fast so don't contribute much to overall delay.

 

Avrum

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Teacher drjohnsmith
Teacher
1,341 Views
Registered: ‎07-09-2009

Re: another question about speed grade

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Can I ask what your up to with delay lines inside the fpga ?

 

I ask as it has come up in the past, and often it turned out they did not real want to use delays,

 

The only real use I have seen is as a very general oscillator, 

 

    so it would be interesting to hear of any other uses ,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor rocky_dm
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Registered: ‎10-25-2018

Re: another question about speed grade

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you are right @drjohnsmith

and thank you again @avrumw

 

I also used Tapped Delay Lines in oscillators,

now I m using TDLs for a time to digital converter project.

 

best regards

 

 

 

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Visitor rocky_dm
Visitor
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Registered: ‎10-25-2018

Re: another question about speed grade

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I m sorry, maybe i should change my question in this manner:

 

does a change in the speed grade mean a change in the overall transistors sizes and performance?

and so, for sure, also in the delays of all carry signals?

 

or the transistor sizes are the same and a change in the speed grade only implies a statistical problem, maybe in a subpart of the die, and, for this reason, the device classified with a low speed grade, did not pass maximum performance tests?

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Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: another question about speed grade

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speed grade is typically a bucketing operation

 

if you have a -3 part it will  work at -3 speed,

if you have a -1 part it will  work at -1 speed,

 

 

BUT,

 

and for you it could be of interest

 

you could be lucky , and a particular  -1 part , could actually run as fast as a -3 part,

  

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Guide avrumw
Guide
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Registered: ‎01-23-2009

Re: another question about speed grade

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Different speedgrade parts are all identical design. The manufacturing process introduces some variability into the performance characteristics of the transistors. Each die coming off the line is tested; if it is fast enough it is categorized as -3, if it is not fast enough for a -3 but fast enough for a -2 it gets categorized as a -2, if it fails that and is still fast enough for a -1 it is categorized a -1. (If it is slower than that it is discarded).

 

Avrum

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Visitor rocky_dm
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Registered: ‎10-25-2018

Re: another question about speed grade

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In conclusion, a low speed grade does not mean a low propagation speed for ALL switching signals, so even for ALL the carry8 chain signals.

 

A low speed grade implies a statistical variation in the process of fabrication somewhere in the die.

This variation could bring maybe only some signal, located in a specific subarea of the die, to have a lower propagation speed or an higher propagation delay.

 

Anyway, this could be like a bottle neck for the whole device that does not pass max frequency working tests for the next speed grade (e.g. -2).

 

So the device is classified with a low speed grade (e.g. -1) because it pass only the tests for the working frequencies of this speed grade.

 

please tell me if i m wrong/right so i can accept a solution.

 

thank you again for help
best regards

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Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: another question about speed grade

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think you have the jist

 

speed grading is statistical as you say

 

as to if one part of a chip can be better than another,

   I doubt , I'd guess all areas are the same wafer,   

      and statistically across a wafer, their is uniformity,

 

Also remember the rigours of sales,

 

its not un known in the industry for say a -3 chips to be branded as -2 chips 

   

qed, you can only say that the chip will meet the specs you purchase,

     its liable to be faster,

 

 

 

       

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Guide avrumw
Guide
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Registered: ‎01-23-2009

Re: another question about speed grade

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as to if one part of a chip can be better than another,

   I doubt , I'd guess all areas are the same wafer,

 

There is definitely some variation on a die - the timing engine even takes this into account. It is by no means as extreme as the variation from wafer to wafer (or more accurately lot to lot), but, nonetheless there is variation.

 

Take a look at this post on how the timing engine deals with on-chip variation.

 

Avrum

 

 

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