axi_c2c with selectIO

[amitg]

Hi,

I have a problem using axi_c2c with selectIO interface. This is the error I get in implementation:

[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/single_end_clk_gen.ibufg_clk_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y8 (in SLR 0)
i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/gen_mmcme3.mmcm_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y0 (in SLR 0)

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/bufg_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y22 (in SLR 0)

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/gen_mmcme3.mmcm_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y0 (in SLR 0)
i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/fb_bufg_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y23 (in SLR 0)

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and i_system_wrapper/system_i/axi_chip2chip_0/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/axi_chip2chip_clk_gen_inst/fb_bufg_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y23 (in SLR 0)

What can I do with this error?

Thanks,

Amit

[dpaul24]

@amitg,

The answer is there is the message itself--

As a workaround for this error, please insert a BUFG in between the IO and the MMCM.

Have you tried this approach? Did it work?

There are more solutions, please read the following answer records:

https://www.xilinx.com/support/answers/62868.html

https://www.xilinx.com/support/answers/66659.html

[amitg · Accepted solution]

The problem was that Rx clk of the interface placed to non GC I/O