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Visitor grinaldi
Visitor
182 Views
Registered: ‎10-28-2015

flip-flop with clear and preset

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Hello,

Is it possible to instantiate directly in verilog a flip-flop that has simulaneosly clear and preset?

Based on UG574 pag 45 it look slike is possible but it doesn't say how:

"IMPORTANT: Using both asynchronous clear and preset on the same flip-flop requires additional
resources and timing paths".

 

Thanks,

Giacomo

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1 Solution

Accepted Solutions
110 Views
Registered: ‎01-22-2015

Re: flip-flop with clear and preset

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Giacomo,

There is no register in UltraScale with both PRE and CLR.  So, instantiation of such a component is not possible. 

However, you can write your HDL in a way that infers a circuit which acts as a register with PRE and CLR.  VHDL that infers this circuit is:

      P1: process(PRE,CLR,CLK)
        begin  
            if(PRE = '1') then
                Q <= '1';
            elsif(CLR = '1') then
                Q <= '0';
            elsif rising_edge(CLK) then
                Q <= D;
            else
                Q <= Q;
            end if;           
    end process P1;  


The Vivado implemented circuit for the above VHDL is shown below (within the red boundary) and consists of 2 LUTs, 2 registers, and a latch.  It is (as Avrum says), kinda ugly.
REG_wPRE_CLR_3.jpg

Mark

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2 Replies
Historian
Historian
145 Views
Registered: ‎01-23-2009

Re: flip-flop with clear and preset

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The short answer is "don't do this". The flip-flop itself is not capable of both a preset and a clear.

It is possible to add additional stuff around the flip-flop to "mimic" the behavior of the missing control signal - I remember seeing what the extra logic is, but can't find it now. I remember it being pretty ugly - I can't remember if it needed a latch (in addition to the flip-flop) to implement the second control signal, or if it did some gating of the clock (ORing the missing control signal into the clock to force it to update). But whichever it is, it is ugly and shouldn't be used.

Avrum

111 Views
Registered: ‎01-22-2015

Re: flip-flop with clear and preset

Jump to solution

Giacomo,

There is no register in UltraScale with both PRE and CLR.  So, instantiation of such a component is not possible. 

However, you can write your HDL in a way that infers a circuit which acts as a register with PRE and CLR.  VHDL that infers this circuit is:

      P1: process(PRE,CLR,CLK)
        begin  
            if(PRE = '1') then
                Q <= '1';
            elsif(CLR = '1') then
                Q <= '0';
            elsif rising_edge(CLK) then
                Q <= D;
            else
                Q <= Q;
            end if;           
    end process P1;  


The Vivado implemented circuit for the above VHDL is shown below (within the red boundary) and consists of 2 LUTs, 2 registers, and a latch.  It is (as Avrum says), kinda ugly.
REG_wPRE_CLR_3.jpg

Mark

View solution in original post

Tags (1)