high-speed serial I/O

[behnam_2705new]

I have a serial Async I/O( rate of data is 622.08 Mbit/s).  I am familiar with HSSIO Ip core. but the input rate is bounded from 800 to 1200 Mbit/s.

My data rate is less than this boundary. what should I do to capture my data correctly? (I have KCU105)

[borisq · Accepted solution]

hi @behnam_2705new 

below is an application on KCU105 with a FMC loopback card.

https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf

This is for synchronising clocking.

For async clocking design, you need to use oversampling.

Below is an application targeting 7 series for your reference.

https://www.xilinx.com/support/documentation/application_notes/xapp523-lvds-4x-asynchronous-oversampling.pdf

Thanks,

Boris

[behnam_2705new]

Do you mean that I can not use I/O in native mode? by instancing primitive cell, like RX_BITSLICE, for this scenario?

[drjohnsmith]

sound slow,  are you using a 'normal' IOB pin, in serial mode, or one of the GTH serdes blocks,

[behnam_2705new]

I am not using GTH block, I want to capture a data from I/O. first of all, HSSIO absorbed my attention, but after reading PG188 and XAPP1274, I realize that I cannot use this IP for my scenario, my data rate is less than the boundary that HSSIO's PLL wants. I want to use I/O from HR, HP or HD banks. 

[drjohnsmith]

I think you need XAPP1064 and XAPP585

[behnam_2705new]

I should have mentioned that I prefer to use native mode and my data is in ASYNC mode, Clock does not come into the FPGA with data. I have LVDS data input with a rate lower than 800 Mhz. (like STM-1 155 Mhz and STM-4 622 Mhz) .

two application note that is mentioned by you is about source synchronous and using SERDES primitives. ( as you know SERDES primitive is a part of component mode I/O), Xilinx shows in https://www.xilinx.com/video/fpga/using-io-in-native-mode-vs-component-mode.html that using I/O in native mode is better than the component mode because of their architecture in the Ultrascale boards. 

[drjohnsmith]

@behnam_2705new 

thanks, when I get to amachine I can give kud on, I will.

its an interesting technique, and new to me, so I'm keeping an eye on it.

     is the speed limit the IO, or the MMCM ?

          if tis the MMCM, can you run it at twice the clock rate , and divide by two on the clock outputs of the MMCM ?

[behnam_2705new]

If I understood correctly this limitation is because of the PLL input clock. In the HSSIO Ip core PLL clock is dedicated and we cannot use the MMCM(MMCM exist in a native mode I/O block ) because of some issue that Xilinx wants to do for high-rate signals(like dedicate clock routing).

[drjohnsmith]

Do u have link to this core please .

Interesting .

[behnam_2705new]

Hi @drjohnsmith, Thanks for your Kudos.

This is a documentation for  HSSIO Ip core

https://www.xilinx.com/support/documentation/ip_documentation/high_speed_selectio_wiz/v3_4/pg188-high-speed-selectio-wiz.pdf

Xapp1330 is documentation that describes Asynchronous Data Capture Using the High-Speed SelectIO Wizard

https://www.xilinx.com/support/documentation/application_notes/xapp1330-async-data-capture-hssio.pdf

Xapp1274 is documentation that describes Native High-Speed I/O Interfaces

https://www.xilinx.com/support/documentation/application_notes/xapp1274-native-high-speed-io-interfaces.pdf

excuse me @borisq  don't you have an idea to capture data below HSSIO rate boundary by using native high speed I/O interface?

[drjohnsmith]

Thank you

Im always amazed, been in the business 40 years, started FPGA's with the Xilinx 3000 series, still finidng new things that they have in them !

Time for a long read,