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xiaoguoer
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Registered: ‎10-29-2020

how can I implement a cache (512 bits * 72) with just one blockram(36Kb)

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it seems 72 bits * 512 can be implemented by only one blockram.
But 512 bits * 72 consumes 7.5 blockram.

board is KCU1500.

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535 Views
Registered: ‎01-22-2015

@xiaoguoer 

As described on page 7 of UG573(v1.11) for 36Kb Block RAM (BRAM), the configuration options are limited to 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18 or 1K x 36 (when used as true dual-port (TDP) memory).   If you try any of these configurations in the Block Memory Generator (see document PG058) then the summary page of the wizard will report utilization of 1ea 36K BRAM.

I can see that your configuration, (72 x 512), results in utilization of 7.5ea 36K BRAM because is is not one of the allowed configurations for a single BRAM.

Cheers,
Mark

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2 Replies
536 Views
Registered: ‎01-22-2015

@xiaoguoer 

As described on page 7 of UG573(v1.11) for 36Kb Block RAM (BRAM), the configuration options are limited to 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18 or 1K x 36 (when used as true dual-port (TDP) memory).   If you try any of these configurations in the Block Memory Generator (see document PG058) then the summary page of the wizard will report utilization of 1ea 36K BRAM.

I can see that your configuration, (72 x 512), results in utilization of 7.5ea 36K BRAM because is is not one of the allowed configurations for a single BRAM.

Cheers,
Mark

View solution in original post

u4223374
Advisor
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Registered: ‎04-26-2015

@xiaoguoer Is it possible that you've got depth and width swapped? If it's trying to make a RAM 512 bits wide then that will take 7 72-bit wide RAMs (ie a BRAM in SDP mode) to get 504 bits, plus a 36-bit wide RAM (ie half a BRAM in SDP mode).