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816 Views
Registered: ‎07-23-2019

how does OSERDESE3 work for DDR/ SDR?

I want to use OSERDESE3 on a Zynq Ultrascale+. UG974 page 498 states:

Attribute   Type  Allowed Values   Default   Description
ODDR_MODE STRING "FALSE","TRUE" "FALSE" Internal property for Vivado primitive mapping. Do not modify.

So how does one specify whether is DDR or SDR?

 

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789 Views
Registered: ‎07-23-2019

@pthakare 

That makes me think... is DDR/SDR respect to the input? to me, the input is 8 bits per input clock period, i.e. SDR.

I've tried different cases and noticed output is always DDR

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pthakare
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Registered: ‎08-08-2017

Hi @archangel-lightworks 

If i presume correctly you have Parallel data (8 bits)  synchronous to clock  (this clock is CLK_DIV here)

what is DATA_WIDTH attribute set to ?

The OSERDESE3 can serialize an outgoing signal by a 2 or 4 in SDR mode, or by a 4 or 8 in DDR mode. When used with SDR clocking, the DATA_WIDTH attribute is to be set to twice the desired width and data to be transmitted should be applied to two pins at a time

x8 in SDR mode is not supported.  follow below table for proper connection and DATA_WIDTH attribute setting

Capture.PNG

additionlly please refer to OSERDES section of UG571 -. page 165 onward on detailing of OSERDESE3

https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

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