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Newbie
Newbie
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Registered: ‎01-27-2020

incorrect range check for IDELAYE3 REFCLK_FREQUENCY ?

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Hi, I am using the IDELAYE3 (and ODELAYE3) with REFCLK_FREQUENCY set to 200. I am getting the simulation error: Error: [Unisim IDELAYE3-109] REFCLK_FREQUENCY attribute is set to 200.000000. Legal values for this attribute are 300.0 to 2667.0. But UG974 (Version 2018.3 and 2019.2) specifies the allowed range from 200 to 2667 MHz Which range is correct ?
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Moderator
Moderator
323 Views
Registered: ‎08-08-2017

Hi @jkayser 

As IDELAYE3 and ODELAYE3 primitives applicable for Ultrascale and ultrascale+  Devices ,UG974 specifies the range for Ultrascale.

The best approroach is to check the Input/Output Delay Switching Characteristics  in datasheet of device you are using ,  Here it seems you are using Ultrascale+ device and range is

300.0 to 800MHZ   (Reference clock frequency for IDELAYCTRL (component mode))

https://www.xilinx.com/support/documentation/data_sheets/ds923-virtex-ultrascale-plus.pdf   -> page 37

I will make a note and report developement team to specify the range in UG974 correctly for ultrascale and ultrascale+  devices.

 

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Reply if you have any queries, give kudos and accept as solution
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Highlighted
Moderator
Moderator
324 Views
Registered: ‎08-08-2017

Hi @jkayser 

As IDELAYE3 and ODELAYE3 primitives applicable for Ultrascale and ultrascale+  Devices ,UG974 specifies the range for Ultrascale.

The best approroach is to check the Input/Output Delay Switching Characteristics  in datasheet of device you are using ,  Here it seems you are using Ultrascale+ device and range is

300.0 to 800MHZ   (Reference clock frequency for IDELAYCTRL (component mode))

https://www.xilinx.com/support/documentation/data_sheets/ds923-virtex-ultrascale-plus.pdf   -> page 37

I will make a note and report developement team to specify the range in UG974 correctly for ultrascale and ultrascale+  devices.

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post