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mojc_mos2
Observer
Observer
11,004 Views
Registered: ‎02-26-2016

limit route of the design to specific region

Hi,

How can i limit my design to specific region in the same region that exist my IOBs ?

best regards

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6 Replies
austin
Scholar
Scholar
11,001 Views
Registered: ‎02-27-2008

m,

 

Easiest way is to use a timing constraint.

 

Why do you care what the tools do?

Austin Lesea
Principal Engineer
Xilinx San Jose
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mojc_mos2
Observer
Observer
10,985 Views
Registered: ‎02-26-2016

I am using vivado 2015 and zynq-7000 . I am beginer to xilinx. I want limit my design to region that i use idelay/iserdes. How can i do this? Can you say key commands?

Regards

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austin
Scholar
Scholar
10,983 Views
Registered: ‎02-27-2008

m,

 

You are posting in the wrong place Zynq 7 series is not UltraScale.

 

You may wish to read::

 

http://www.xilinx.com/applications/isolation-design-flow.html

 

and

 

https://forums.xilinx.com/t5/Implementation/How-to-lock-placement-for-Vivado-design/td-p/517367

Austin Lesea
Principal Engineer
Xilinx San Jose
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vemulad
Xilinx Employee
Xilinx Employee
10,946 Views
Registered: ‎09-20-2012

Hi @mojc_mos2

 

You can use pblocks to restrict the placement of the logic to specific region in FPGA.

 

Refer to below links

from page-170 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug906-vivado-design-analysis.pdf

and video http://www.xilinx.com/video/hardware/design-analysis-floorplanning-with-vivado.html

Thanks,
Deepika.
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mojc_mos2
Observer
Observer
10,899 Views
Registered: ‎02-26-2016

ok. many thanks for your assistance. 

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vemulad
Xilinx Employee
Xilinx Employee
10,852 Views
Registered: ‎09-20-2012

@mojc_mos2

 

Feel free to close the thread by marking the solution.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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