03-01-2016 09:22 AM
How can i limit my design to specific region in the same region that exist my IOBs ?
03-01-2016 11:42 AM
I am using vivado 2015 and zynq-7000 . I am beginer to xilinx. I want limit my design to region that i use idelay/iserdes. How can i do this? Can you say key commands?
03-01-2016 11:45 AM
You are posting in the wrong place Zynq 7 series is not UltraScale.
You may wish to read::
03-01-2016 10:57 PM
You can use pblocks to restrict the placement of the logic to specific region in FPGA.
Refer to below links
03-03-2016 10:19 PM
Feel free to close the thread by marking the solution.