04-01-2019 02:18 AM
Hello.I want to use ODDR to forward a clock as an output, which will drive another XCVU13P. I wonder if the driving capacity is enough for anthor FPGA? I also want to konw is there a delay betweent the outputing clock and the source clock.? Thank you .
04-01-2019 02:47 AM - edited 04-01-2019 02:48 AM
using the ODDR is the normal way to do this sort of thing.
Use a fast differnetial signal like LVDS between the FPGAs is a good tip as well.
As for the more general question of phase / clocking.
thats VERY big one.
The optoins are
a) ignor and hope,
b) send clock with data between the fpgas, and re syncronise on the fpga
c) use the PLL's in the FPGAs to cancel out the delay
this is an old note, fig 11 might be of help
Note to adminstrators if they are on line:
These old app notes and techniques are in danger of being missed, as people looking at modern chips would not look at or for these old docs.
04-02-2019 11:04 PM
@drjohnsmith sorry. but i dont understand the second way using LVDS between FPGAs.In my opinon, every pin can be used as clock-outputing pin and I must use ODDR to keep the duty cycle and provide the best possible path.Does your second way mean that we can give a lvds clock directly to anthor FPGA without using ODDR?
04-03-2019 08:30 AM
LVDS. Is a normaly differential logic standard,
ODDR. is a Xilinx primative in the chip , output Double Datarate register
What format you select to send clock out / in on is up to you, I'd normaly select differential LVDS, is very reliable.
same goes for data
have a look here,
04-03-2019 11:46 PM
04-04-2019 12:34 AM
LVDS is the IO standard of the pins.
ODDR is a primative inside the fpga used to register