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fanwei
Adventurer
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Registered: ‎05-29-2015

the relationship between PL_CLK and m_axi_clk when in ZCU111 Multi RF-ADCs tiles synchronization ?

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Hi,

    There is a question for me  when for Multi RF-ADCS tiles synchronization.  

    in pg269 (v2_4 ) page176,when adc and dac working  on different clock rates,the PL_CLK must be common multiple or sub-multiple of the          RF-ADC andRF-DAC AXI4-Stream clocks,show below:

   but when only using multi-ADCs Tile, the PL_CLK is also be common mulitple or sub-multiple RF-ADC AXI4-Streams clk?

      

fanwei_0-1623313192875.png

 

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pthakare
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397 Views
Registered: ‎08-08-2017

Hi @fanwei 

With these frequency values , PL SYSREF frequency is common sub-multiple of all the clocks in the system. 

But PL_CLK is not  common multiple or sub-multiple of the RF-ADC AXI4-Stream clock.

I will discuss internally if you this works for MTS or having the PL_CLK common multiple or sub -multiple of the RF_ADC Stream clock is stringent requirement and that need to followed strictly.

 

 

 

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fanwei
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Registered: ‎05-29-2015

in my project,my adcs  working on sample rate 3.328Gsps. real-->I/Q   2xDecimation with NCO. So need  axi-stream clk is 208M. 

i will using LMK04208(VCO freq :3072Mhz) generate 8M analog SYSREF and PL_SYSREF, but I can not config clk divider in LMK04208 to generate PL_CLK that mulitple or sub-multiple of the axi-stream clk,

i will try to generate 96M  PL_CLK   and  use a mmcm in fpga  to generate 208M  to axi-stream clk

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pthakare
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Registered: ‎08-08-2017

Hi @fanwei 

With these frequency values , PL SYSREF frequency is common sub-multiple of all the clocks in the system. 

But PL_CLK is not  common multiple or sub-multiple of the RF-ADC AXI4-Stream clock.

I will discuss internally if you this works for MTS or having the PL_CLK common multiple or sub -multiple of the RF_ADC Stream clock is stringent requirement and that need to followed strictly.

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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fanwei
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Registered: ‎05-29-2015

thank you  @pthakare  .

   So in my project , the LMK04208 can not generate the PL_CLK that is common multiple or sub-multiple of the RF-ADC AXI4-Stream clk. 

   There is no guarantee that Multi RF-ADCs tiles synchronization.

   In another way,when  ADCS or DACS   sampling frequency is set strangely ,but LMK04208  can not generate the correct  sysref and PL_CLK frequency, it will fail when synchronization is         performed, 

  Is there a solution here for applications with   setting strangely frequency?

 

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fanwei
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Registered: ‎05-29-2015

hi @pthakare 

   i  have configured the LMK04208 PLL2  paramenter to  modify interal VCO  freq,and generated the PLL_CLK and analog SYSREF PL_SYSREF that i wanted,

    and these freq are sub -multiple of the RF_ADC sample clks/ axi-stream clk