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anusua.das9@gmail.com
Contributor
Contributor
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Registered: ‎08-14-2019

uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

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I use the FPGA part xczu4ev Mercury Enclustra board. And I try to use example IP design for the uhdsdi - gt and RX (receiver) system. I have the following error when I run implementation:

[Route 35-54] Net: i_design_1/design_1_i/uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

What can be the possible solution? How to debug it?

Unbenannt1.PNG
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roym
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Registered: ‎07-30-2007

I see on this chip there is only one quad.  It is not possible to use the north/south refclk inputs.  You have a refclk from the quad you're in trying to drive a southrefclk port. 

Drive gtrefck1 with the SI5324 input as it is now and drive gtrefclk0 with the SI570 input.

On the GT common the SI570 should drive GTREFCLK00 and GTREFCLK01.

 




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roym
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Registered: ‎07-30-2007

Can't say for sure what the problem is with just this information.  To use the reference clock pins to drive a recovered clock off the chip use the OBUFDS_GTE4 primitive.  It looks like you may have tried to do this with something else.  Similarly the refclk input would drive the GT  southrefclk through a IBUFDS_GTE4 primitive.  If there is only one refclk input and you will not be dynamically changing refclk's you would drive the gtrefclk0 pin and set the *refclksel to 001.  Vivado will take care of the rest.  Also these are all things normally taken care of in the example design.  Are you using the example design?




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anusua.das9@gmail.com
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Contributor
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Registered: ‎08-14-2019

I am using the example design. While importing the design, some parts of the FPGA board did not match, and after completing the Report_ip_status, when I run implementation, this error appears. Also, I am using Vivado 2018.2

Please find the dcp file

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roym
Moderator
Moderator
506 Views
Registered: ‎07-30-2007

I see on this chip there is only one quad.  It is not possible to use the north/south refclk inputs.  You have a refclk from the quad you're in trying to drive a southrefclk port. 

Drive gtrefck1 with the SI5324 input as it is now and drive gtrefclk0 with the SI570 input.

On the GT common the SI570 should drive GTREFCLK00 and GTREFCLK01.

 




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


View solution in original post