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Anonymous
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updatemem is not working with Kintex Ultrascale

 

I have a 8192x32 Block RAM in my design. I would like to update this memory without reimplementing the design. So I planed to use updatemem utility to update bit file with mem file. With the help of answer record http://www.xilinx.com/support/answers/63041.html I have done this successfully for Kintex7 architecture. But for Ultrascale architecture it is failing. In Ultrascale architecture this memory is created using Seven RAMB36E2 BLOCK RAM module and One RAMB18E2 BLOCK RAM module. And Cascading is also used. Can anybody help me to generate a .mmi file for this 8192x32 LOW_LATENCY RAM.

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Anonymous
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When I am running updatemem command I am getting the following error "line 164: 13174 Segmentation fault "$RDI_PROG" "$@"" Anybody have any Idea.

 

When I am updating 15-0 bits of BRAM this error is not coming. When I try to update 17-0 of the same BRAM this error comes.

 

the BRAM is get configured as data15-0 connected to DINADIN[15:0] and data 17-16 connected to DINPADINP[1:0].

 

Currently my mmi file lool like below. if it wrong please let me know.

 

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
    <AddressSpace Name="ROM8192X32" Begin="0" End="32767">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y4">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y5">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="2048" End="4095"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y6">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="4096" End="6143"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y7">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="6144" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
  </Processor>
  <Config>
    <Option Name="Part" Val="xcku040-ffva1156-2-e"/>
  </Config>
</MemInfo>

Updatemem error details given below:

 

updatemem -force --meminfo ROM8192X32_17-0.mmi --data bram_17-0.mem --bit ../vivado/mem_init.runs/impl_1/bram_ini_topmodule.bit --proc dummy --out download_17-0.bit

****** updatemem v2015.3 (64-bit)
**** SW Build 1368829 on Mon Sep 28 20:06:39 MDT 2015
**** IP Build 1367837 on Mon Sep 28 08:56:14 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source /tooltop/vendor/xilinx/Vivado_2015.3/Vivado/2015.3/scripts/updatemem/main.tcl -notrace
/tooltop/vendor/xilinx/Vivado_2015.3/Vivado/2015.3/bin/loader: line 164: 13174 Segmentation fault "$RDI_PROG" "$@"

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pratham
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Registered: ‎06-05-2013

@Anonymous Is it possible to check with 2015.4 version of the vivado tool?

-Pratham

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Anonymous
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I have built using 2015.4 but I am still getting the same error line 164: 29543 Segmentation fault      "$RDI_PROG" "$@"

 

When I change the mmi file parity tag from this <Parity ON="false" NumBits="0"/> to <Parity ON="false" NumBits="2"/> then this error has gone.

The new mmi file is giving here. But still the data is not correct when I read back after downloading a updated bit file using updatemem. 

Could you explain how to write mmi file incase of Data is sharing between datainput line and parity input lines of BRAM.

In this case 15:0 of data is connected to DINADIN[15:0] and 17:16 of data is coinnected to DINPADINP[1:0] of RAMB36E2 and four of these RAMB36E2 has been cascaded to get 8192 Depth (32KB).

 

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="dummy">
    <AddressSpace Name="ROM8192X32" Begin="0" End="32767">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y4">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="2"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y5">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="2048" End="4095"/>
          <Parity ON="false" NumBits="2"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y6">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="4096" End="6143"/>
          <Parity ON="false" NumBits="2"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X7Y7">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="6144" End="8191"/>
          <Parity ON="false" NumBits="2"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
  </Processor>
  <Config>
    <Option Name="Part" Val="xcku040-ffva1156-2-e"/>
  </Config>
</MemInfo>
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Anonymous
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11,114 Views

Schematic of BRAM after synthesis

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Anonymous
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11,003 Views

How can I specify data bits connected to Parity lines of BRAM in the mmi file?

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Anonymous
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10,789 Views

My problem is Vivado synthesis is using Parity pins of BRAM for DATA lines.

I want to tell the vivado synthesis tool not to use parity lines of BRAM for data lines. 

 

That is the synthesiser can use as many as BRAMs but not use PArity lines for Data.

 

Anybody can tell me any synthesis directive for not use parity lines for data when inferring RAM using BRAM.

 

 

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Anonymous
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10,787 Views

@pratham could you please help me.
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