10-10-2019 03:41 AM
For a project I need to bring 600 MHz clock to a Kintex XKU040, because the doughter bord will be
connected with an LPC FMC connecter I can use FMC_LPC_CLK0_M2C that goes to HP 47 IO_L12_GC on the FPGA or
or FMC_LPC_LA00_CC that goes to HP 47 IO_L13_GC on the FPGA.
I want to read 16 bits of data htat are comming to the FPGA syncronized with this clock. M2C is a Global Clock pin
and CC is a clock capable pin, which one I should select for this application.
the next question is that if I use CC then can I connect it to the MMCM to make a lower frequency clock from it or not.
Thanks for your help.
10-10-2019 04:03 AM
Your connecting to a data bus at 600 Ms/s
thats going to be fun,
any slight difference in the track lengths / connector phase match is going to kill your chances of grabbing clean data.
Your probably going to require you to use the i_delay blocks and tunning to try to grab the clear eye of the data .
You might have to impliment the asyncronous technique where by the clock in is treated as just a reference signal for the data
Id strongly suggest you impliment an FPGA design before you commite to layout,
that will answer what clocking scheme you need to use .
10-10-2019 04:57 AM
Thanks for your reply,
But I still didn't get the answer of my question.
Can I use Global Clock for this reason or I have to use Clock capable pairs only?
10-10-2019 05:18 AM
for your application, I recommend seeing the HSSIO wizard.
capturing 600 Mbit/s data its not an easy project.
you should consider timing, delay, and clock difference that both transceivers have.
in native I/O you can drive the clock with both GC and CC, which based your Bitslice and bank and how you configure that.
Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
10-10-2019 07:29 AM
The answer is there,
You can use any combination of clock pins / MMCM / PLL
the deisng is still not going to work as you describe it, due to the reasons we have described to you.
We also suggetsed to you that you try the desingout in an FPGA, see if it meets timing,
it only has to the the top level IO part of the design,
Different chips have very different clock capabilities, routing resources,
and the only definitive way to know any clocking answers is to try it out .
Let us knwo how you get on with the trial design and the simulatoin / fitter / timming constraints.
Once you have a frame work of an idea post a new toppic and we might be able to help you a little more.