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jmcm
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Registered: ‎06-25-2018

12-bit per component Gamma Correction LUT

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Hello,

Xilinx has a Gamma Correction IP supporting up to 12-bit per component (PG004).which is now discontinued.

It is being replaced by the LogiCore Gamma LUT (PG285) which only goes up to 10-bit per component.

Does this mean that a Gamma LUT with 12-bit per component is not provided any longer?

Regards.

Jmcm

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florentw
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Registered: ‎11-09-2015

HI Jacques,

Do you have any update on this? Were you able to write you own IP with HLS?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @jmcm ,

Yes your understanding seems correct.

If 12-bit support for gamma correction LUT is a requirement for you, I encourage you to contact your FAE about this to see if this can be implemented in future releases.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jmcm
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Registered: ‎06-25-2018

Hi Florent,

Yes, 12 bits per component, 2 pixels per clock, 300MHz.

Thanks,

Jacques

 

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florentw
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Registered: ‎11-09-2015

HI @jmcm 

Then please contact your FAE about this.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jmcm
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Registered: ‎06-25-2018

Hello Florent,

I started on the design of the LUT as I need to progress in my project.  I am using 3 xpm_memory_tdpram with a read latency of 1 made out of ultra-rams to get 2 pixels per clock.

The axi-lite interface to program the LUTs is straight forward.  But I'm having problems with the axi-stream master and slave interfaces.

One way maybe to do this is to duplicate the URAMs to avoid creating bubbles in the stream but I would rather stay with 3 if possible.  Could you please point me to some docs or template codes to do this if there is any.

Regards,

Jacques

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florentw
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Registered: ‎11-09-2015

Hi Jacques @jmcm 

Did you consider using HLS for this? What I found great with this is that you do not have to really care about the AXI4-Stream interface. You just say "read or write" data. It might save you same headhache

I made an example of video IP as part of my video series: Video Beginner Series 17: Create a Video Crop IP using HLS (part 1) and Video Beginner Series 18: Create a Video Crop IP using HLS (part 2)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jmcm
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Registered: ‎06-25-2018

Thanks Florent,

I'll look into it.

Jacques

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florentw
Moderator
Moderator
709 Views
Registered: ‎11-09-2015

HI Jacques,

Do you have any update on this? Were you able to write you own IP with HLS?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

jmcm
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Registered: ‎06-25-2018

Hello Florent,

I was able to write a verilog module to handle this.  I will try HLS when I have more time.

Thanks,

Jacques