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Adventurer
Adventurer
260 Views
Registered: ‎07-29-2019

2 MIPI CSI-2 Rx Subsystem IP in the same HP I/O bank

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Hi Team,

We are using 2 MIPI CSI-2 RX Subsystem IP in the design targeting xczu7cg-fbvb900-1-e device and vivado version is 2019.2. 

Both the IPs are in the same HP bank(Bank 64). We have tested the design with both the IPs in 800Mbps line rate and we are not finding any CRC or ECC errors. The number of lines and pixels are constant as expected.

But when we try testing in higher line rates(2000Mbps), we are getting CRC and ECC(2 bit) errors and also the number of lines and pixels are not constant.

Before checking the hardware for the above errors, I just want to make sure that the configuration of IP in the GUI is proper.

And also I want to know is there any consideration when use 2 MIPI IPs in the same HP bank.

I have attached the pin configuration of the 2 MIPI IPs.

 

Capture_comm_1.PNG

Capture_comm_2.PNG

 

have also attached the .xci files of the 2 MIPI IPs and bd.tcl for the block diagram of the design.

Do we need to connect clkoutphy_out signal in the design. Currently this is not connected anywhere in the design

 

Capture_comm_3.PNG

Please let me know if there any changes needs to be done in the IP settings and the block diagram for the higher line rates.

With regards,

Thejashree

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Xilinx Employee
Xilinx Employee
230 Views
Registered: ‎03-30-2016

Hello @thejashree_13 

I do not see any issue on the MIPI CSI-2 RX IP setting.

MIPI_RX_2000_SETTING.png

For line-rate above 1500Mbps, please enable Deskew pattern feature on your sensor.
Could you please check AR#73209 ?
The length of the periodic deskew pattern sent by the transmitter should match the requirement of the receiver side.
Xilinx MIPI D-PHY RX deskew algorithm requires a minimum of 8192 UI (or 1024 rxbyteclockhs) of periodic deskew-pattern to do calibration correctly. Please confirm that your sensor is configured correctly.

>Do we need to connect clkoutphy_out signal in the design. Currently this is not connected anywhere in the design

No, since your IP is configured as "Include Shared Logic in core"

Regards
Leo

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎03-30-2016

Hello @thejashree_13 

I do not see any issue on the MIPI CSI-2 RX IP setting.

MIPI_RX_2000_SETTING.png

For line-rate above 1500Mbps, please enable Deskew pattern feature on your sensor.
Could you please check AR#73209 ?
The length of the periodic deskew pattern sent by the transmitter should match the requirement of the receiver side.
Xilinx MIPI D-PHY RX deskew algorithm requires a minimum of 8192 UI (or 1024 rxbyteclockhs) of periodic deskew-pattern to do calibration correctly. Please confirm that your sensor is configured correctly.

>Do we need to connect clkoutphy_out signal in the design. Currently this is not connected anywhere in the design

No, since your IP is configured as "Include Shared Logic in core"

Regards
Leo

View solution in original post

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Adventurer
Adventurer
191 Views
Registered: ‎07-29-2019

Hi @karnanl ,

Thank you so much for the response.

After configuring the sensor for the proper TSKEWCAL value its working fine at the higher line rates.

With regards,

Thejashree

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Xilinx Employee
Xilinx Employee
181 Views
Registered: ‎03-30-2016

Hello @thejashree_13 


That's good to hear. Thanks a lot for the update.

Regards
Leo