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Registered: ‎03-03-2017

2018.1 SDK HDMI Tx with HDCP DP Rx without

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Hi,

   I am working on a design with HDMI TX which uses HDCP 1.4 and 2.2 as well as DisplayPort RX (without any HDCP) and I am having trouble getting SDK to compile the design once I enabled HDCP 1.4 in the HDMI TX.

   I am using Vivado/SDK 2018.1 and a Kintex-7 device on custom hardware.

   It seems that once HDCP 1.4 was enabled in the design, the DisplayPort SDK driver assumes that the HDCP 1.4 applies to it.

   The SDK compile errors are due to finding XPAR_XHDCP_NUM_INSTANCES defined since it is used, but not finding items defined in xparameters.h which would be there if the DisplayPort RX block in the block design was implemented with HDCP.

   Question: Is this something that is solved in 2018.2 drivers/IP?   It would be good to have something in the HDCP setup that defines what blocks in the design will use it.

 

Thanks.

Tim

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Highlighted
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Registered: ‎03-03-2017

My solution is to edit the BSP files shown in the image below to make it work.   I believe Xilinx will work on making this work without needing BSP modifications in a future driver.

hdcp9.png

Tim

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Registered: ‎11-09-2015

Hi @tim_severance,

 

2018.2 is out but I don't think this is solved. I think we never had any customer using this case so we didn't fall into this issue.

 

I sent you a link by email, could you upload your project? I will see what I can do.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw,

   Ok, I was mainly curious if this was something that might have gotten fixed.

   I am able to get it to work by manually editing the BSP files to look for a different HDCP define variable, and I save those edited files so if I ever regenerate the BSP I can copy the edited files back over.

   I also figured I was an extreme case, and most people won't be doing what I am doing.

   Let me know if you still want me to upload the files, otherwise we can close this.

Thanks.

Tim

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Registered: ‎11-09-2015

HI @tim_severance,

 

Yes please send me your test case. Even if it is not a common use case, this is still an issue. So it needs to be fixed.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

HI @tim_severance,

 

In fact correct me if I am wrong but there is an issue because you are using the example design right? The errors are happening in the application not in the driver?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw,

   I am out today so I cannot try it out, but I recall if I regenerated the BSP I got compile errors in the BSP itself and once I resolved those then everything compiled successfully.  

Tim

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Registered: ‎03-03-2017

My solution is to edit the BSP files shown in the image below to make it work.   I believe Xilinx will work on making this work without needing BSP modifications in a future driver.

hdcp9.png

Tim

View solution in original post