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Participant
Participant
1,209 Views
Registered: ‎02-01-2018

2018.2: Problem with TUSER of Ycrcb2RGB converter

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Hello,

 

have a strange behavior of the Ycrcb2rgb converter. It generates second TUSER before the first TLAST will be received from the source. The video chain consists of three blocks: BT656 to Ycrcb422 converter (selfmade), Croma Resampler IP and Ycrcb2rgb converter. The PLA video signal has 720 pix per line and 288 lines per frame in interlaced mode.

video chain

Chroma resampler and Ycbcr2rgb converter will be hold in reset so long the video input will be configured. BT656 converter waits for the beginning of the first odd field and start with TUSER as SOF and TLAST at the end of each line. ILA measurement confirms, that exactly 720 Ycbcr-422-words are valid per line.

Netherless Ycbcr2rgb converter generated dual TUSER at the beginning of the first line, and wrong TLAST after that. The status and error register of Ycbcr2rgb read over the AXI-Lite IF (built in later) have values 3 and 0 respectively - no ERRORS!

 

ycbrc_tuser.jpg

 

Ycbcr2rgb config:

 

color_space.JPG

 

Any ideas?

 

 

 

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Moderator
Moderator
1,167 Views
Registered: ‎11-09-2015

HI @patcher33,

 

Fist thing I have to say is that the YCrCb2RGB is obsolete (as the chroma resempler IP). You might want to consider using the Video Processing Subsystem IP instead.

 

With that say, I recently tried the YCrCb2RGB for my Video Beginner Series 9 and I didn't faced this issue.

Could you try in simulation and see if you can reproduce this?

 

Would you be able to share your project with me?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
1,168 Views
Registered: ‎11-09-2015

HI @patcher33,

 

Fist thing I have to say is that the YCrCb2RGB is obsolete (as the chroma resempler IP). You might want to consider using the Video Processing Subsystem IP instead.

 

With that say, I recently tried the YCrCb2RGB for my Video Beginner Series 9 and I didn't faced this issue.

Could you try in simulation and see if you can reproduce this?

 

Would you be able to share your project with me?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Participant
Participant
1,163 Views
Registered: ‎02-01-2018

thank you. we will switch to VPROC

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Moderator
Moderator
1,158 Views
Registered: ‎11-09-2015

HI @patcher33,

 

If you are using the VPSS you might want to start with its example desing. the Vpss requires specific steps in a specific orders to work properly. The driver help you start with using the driver.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant
Participant
1,144 Views
Registered: ‎02-01-2018

Hi,

 

the example design of the V_proc_ss is configured in scale only mode by default. For all tests implemented in the software we changed it to "full pledged", but we would like to test the deinterlacer performance, too.

 

Is it enough to reconfig the timing generator to generate the field_id and connect it to the v_proc_ss, in order to get deinterlacer mode tested?

 

Regards

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Moderator
Moderator
1,133 Views
Registered: ‎11-09-2015

HI @patcher33,

 

The configuration of the VPSS in the example design depends on your configuration of the IP when you generate the example design.

If when you open the example design, the VPSS is configured as full fledge, then the example design will be full fledge

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**