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Registered: ‎04-05-2019

2x 4Lane MIPI RX Pinning over two banks

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Hi there,

We currently try to route a 2 x 4Lane MIPI Bus (2 x (1Clk + 4Data)) to an Artix-7 200T FPGA in the SBG484 Package,
while using the two HR banks 13 and 14 for the LP and HS lines written in xapp894.

Right now I distributed each of the two 4Lanes on a separate bank, so let's say all LP/HS signals of 4Lane A to Bank 13
and all LP/HS of 4Lane B to Bank 14.

However, routing the signals to the banks shows that it would be benefical for the layouting if one differential data line of 4Lane A would be placed in bank 14
and one data line of 4Lane B in Bank 13.

I'm trying to figure out if this would work. Especially the respective clock lines sitting in other banks gives me a headache.
I don't know if the clock distribution in the Artix-7 could handle MIPI D-PHY clocks over separate banks.
I think connecting each clock to a MRCC pin would then be mandatory (instead of SRCC).

Have you any idea/experience if that would work?

Best regards,
Simon

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi simon.braun@sick.de ,

As per pg202 p83, the D-phy IP requires the IO to be placed in a single bank:

MIPI.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
841 Views
Registered: ‎11-09-2015

Hi simon.braun@sick.de ,

As per pg202 p83, the D-phy IP requires the IO to be placed in a single bank:

MIPI.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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831 Views
Registered: ‎04-05-2019

Thank you Florent,

That answers my question!
Haven't had a look on that section.

Best regards,

Simon

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Visitor
Visitor
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Registered: ‎03-11-2019

Hi Florent,

We currently try to route a 1x 4Lane MIPI Bus (1 x (1Clk + 4Data)) in the  Artix-7 200T FPGA,we want to use the MIPI RX-CSI2 Sybsystem IP in our project.

If I distributed the HS signals to bank13 ,and the LP signals to bank14,will the MIPI RX-CSI2 Sybsystem IP work normally?Must all the signals about the MIPI Interface  be in the same bank?

THX.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @wjl3258 

MIPI development team tested 7-series MIPI IPs with pin assignments on a single IO  bank.
For your usecase, using a single IO bank should be sufficient. But if it is required to use multiple IO banks I would recommend to create a test design in Vivado, do implementation and check of any errors.
If Vivado does not show any errors you are good to go.

Thanks & regards
Leo

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Visitor
Visitor
278 Views
Registered: ‎03-11-2019

Hello,Karnanl

Thank you for your reply.I mada a test design in Vivado19.1,and Vivado does not show any errors. 

And I want to connfirm the constrants on the signals.If I choose the compatible solution(axpp894 P15),I set the constraints  for the HS signals are LVDS_25 and  DIFF_TERM  = FALSE in bank13,and the LP signals are LVCMOS12 in bank14.Are the above constraints correct? In the compatible solution,must be the DIFF_TERM = FALSE  for the HS signals? 

Best regards.

 

 

 
 
 

image.png

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @wjl3258 

>I mada a test design in Vivado19.1,and Vivado does not show any errors. 


That is good.

>I set the constraints  for the HS signals are LVDS_25 and  DIFF_TERM  = FALSE in bank13,and the LP signals are LVCMOS12 in bank14.Are the above constraints correct? In the compatible solution,must be the DIFF_TERM = FALSE  for the HS signals? 

If you want to implement compatible solution,
Could you please try to generate MIPI example design for SP701 board ? (see PG232 Chapter 5)
This example design does not enable DIFF_TERM setting for LVDS_25.  (MIPI HS pins)

MIPI_SP701_Exdes.png
Thanks and regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @wjl3258 

I generated MIPI example design for SP701.
Confirmed that no DIFF_TERM enabled added in the XDC file. (File is attached with .txt extension )

Regards
Leo

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