cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
923 Views
Registered: ‎07-28-2020

4K Video transmission using Zynq Ultrascale+ MPSoC

Jump to solution

Hello, 

I recently came across one video from Xilinx, in which they have used Zynq Ultrascale+ MPSoC for 4k video transmission and reception. I want to replicate this project. Any help in this context will be much appreciated.

Regards

Nitin Kumar

Tags (1)
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
787 Views
Registered: ‎08-02-2007

@Nitin_Kumar 

I think the video is talking about VCU TRD Multistream design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/541786229/Zynq+UltraScale+MPSoC+VCU+TRD+2020.1+-+VCU+TRD+Multi+Stream

One of the stream is captured from MIPI camera through framebuffer+PS DDR

View solution in original post

15 Replies
Highlighted
Xilinx Employee
Xilinx Employee
857 Views
Registered: ‎08-02-2007

@Nitin_Kumar 

Which Video did you watch? HDMI FrameBuffer example design supports 4k video transmission and reception : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842753/HDMI+FrameBuffer+Example+Design

If you are not Linux user, you can refer to chapter 6 of https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf, and then generate the passthrough example design with Bare-metal driver.

Highlighted
Observer
Observer
829 Views
Registered: ‎07-28-2020

hello @xud ,

Thank u for your response, I watched this, "New video: Simultaneous 4K video encode/decode over IP using Zynq UltraScale+ MPSoC supporting as many as 8 streams," available at https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/New-video-Simultaneous-4K-video-encode-decode-over-IP-using-Zynq/ba-p/800953.

Thanks for sharing the link, I don't have HDMI IP, so I am working with MIPI CSI.

Regards

Nitin Kumar

0 Kudos
Highlighted
Observer
Observer
823 Views
Registered: ‎07-28-2020
Also I want to transfer data from MIPI Rx subsystem to PS DDR via Frame buffer/VDMA, I want to know the math behind it. Like how to calculate the data rate for different configurations 1,2,3,4 lane Raw8,10,12, how to calculate the bandwidth and also to know whether this bandwidth will be supported by DMA or not. Any link to this will be really helpful.
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
788 Views
Registered: ‎08-02-2007

@Nitin_Kumar 

I think the video is talking about VCU TRD Multistream design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/541786229/Zynq+UltraScale+MPSoC+VCU+TRD+2020.1+-+VCU+TRD+Multi+Stream

One of the stream is captured from MIPI camera through framebuffer+PS DDR

View solution in original post

Highlighted
Observer
Observer
719 Views
Registered: ‎07-28-2020

Hello @xud , sorry for late reply. Thanks for sharing the link and information.

I saw the link that you shared. As you may see that all of these pipelines, converts raw data to RGB and does some processing before dumping data into PS DDR, and also frame buffer does not take raw input. I want to do some ISP before converting raw data into RGB, hence require data directly from MIPI Rx subsystem into PS DDR. And after doing ISP do some more processing in PL using demosaic/GammLUT correction etc.

Can you suggest some design/example/tutorial for this?

Regards

Nitin Kumar

 

Highlighted
Scholar
Scholar
668 Views
Registered: ‎12-07-2018

Hello, were you able to get the project working? Also, did you use an OS?

Thank you

0 Kudos
Highlighted
Observer
Observer
637 Views
Registered: ‎07-28-2020

Hello @joe306 , No I did not try to execute this project as I don't have ZCU102 board, also I am only interested in using MIPI CSI interface. There are other designs available from Mr.Adam Taylor involving MIPI but he uses RGB data (MIPI to Demosaic,GammaLUT) and transfers that into PS DDR, although he has given solutions both with and without OS. My solution requires raw data in PS DDR.

Regards

Nitin Kumar

Highlighted
Teacher
Teacher
614 Views
Registered: ‎06-16-2013

Hi @Nitin_Kumar 

 

Can you use linux OS ?

If yes, would you use GStreamer and v4l2src element to store video stream into PS DDR ?

 

Also, you can see example if you saw @xud 's suggested URL.

 

Best regards,

Highlighted
Observer
Observer
592 Views
Registered: ‎07-28-2020

Hello @watari , My question was more intended towards Hardware development(Vivado pipeline), but yes I intend to use create platform and Linux OS image using .xsa container from Vivado. Also, I am using Gstreamer and v4l2 packages during platform generation, but I am just following few tutorials and don't exactly know the purpose of all the packages that are being used. I have just started learning and using FPGA/Xilinx tools.

Probably if you can illuminate the topic by sharing your knowledge, it will be very useful for newcomers like me.

Regards

Nitin Kumar

Highlighted
Scholar
Scholar
572 Views
Registered: ‎12-07-2018
Your project sounds very interesting. I'm working with SDI Video and CoaXpress Video. I will be interfacing with video cameras and then I will do video overlay and meta-data insertion. Would you be willing share your IP Integrator Block Design? Maybe convert it to TCL for regeneration or convert it to pdf?
Respectfully,
Joe
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎03-30-2016

Hello @Nitin_Kumar 

PS-DDR question should be posted on embedded board rather than Video board here. You will have better response from embedded users.

First, Could you please check the following AR ?
https://www.xilinx.com/support/answers/70413.html

I believe you need to use AXI-DMA to transfer AXI4-stream data from PL to PS-DDR.
This AR will show you an example how to use AXI-DMA IP.

Some of Xilinx TRDs also using AXI DMA in the design. For example :
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/520618122/Zynq+UltraScale+MPSoC+Base+TRD+2020.1

Regards
Leo

Highlighted
Observer
Observer
397 Views
Registered: ‎07-28-2020

Thanks @karnanl ,

     Yes I need to use AXI-VDMA or Frame Buffer to transfer data from PL to PS-DDR, my confusion was if raw data could be transferred or not as most of the examples involve some video processing before pushing data into DDR. But my doubt is clear now, frame buffers can be used to push Y data(raw) into DDR.

Thanks for your answer.

Regards

Nitin Kumar

Highlighted
Scholar
Scholar
376 Views
Registered: ‎12-07-2018
Thank you very much for posting your comments. I will be working with video soon and this will be helpful. Respectfully, Joe
Highlighted
Observer
Observer
369 Views
Registered: ‎07-28-2020

@joe306 I regret that I can't share the vivado pipeline with you right now, as I am still working and it is not yet developed.

Regards

Nitin Kumar

Highlighted
Scholar
Scholar
366 Views
Registered: ‎12-07-2018
That's okay. I'm glad others are doing fun stuff. Respectfully, Joe