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Visitor
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Registered: ‎11-08-2018

A solution to a 16-lane CSI-2 application

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Hello,

We are working with a mmwave radar sensor (TI AWR1243 transceiver).  Now we are evaluating base-band processor solutions. Xilinx Virtex 7 or Ultrascale+ FPGAs is a competitive choice for us. However, we get some confusions.

Each AWR1243 radar sensor has a CSI-2 V1.1 interface with 4 data lanes. We want to use a single base-band processor to handle the data generated by a 4-chip AWR1243 cascaded digital front end. I noticed that Virtex 7 and Ultrascale+ series FPGAs supply CSI-2 controller and D-PHY. But each CSI-2 controller support 4 data lanes. So if we choose one Xilinx FPGA as our processor, shall I just instance four CSI-2 controller IP cores and make corresponding IO selections to handle the 16-lane data from the 4 radar sensors?

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Registered: ‎11-09-2015

Re: A solution to a 16-lane CSI-2 application

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Hi @yingliuysy,

Yes you can use 4 instances of the MIPI CSI2 RX IP to receive data from the 4 radars.

One comment on the device: I would recommend you to go for Ultrascale+ because it has a MIPI termination in the device. For Virtex-7, you would need to use an external phy as mentioned in xapp894.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: A solution to a 16-lane CSI-2 application

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Hi @yingliuysy,

Yes you can use 4 instances of the MIPI CSI2 RX IP to receive data from the 4 radars.

One comment on the device: I would recommend you to go for Ultrascale+ because it has a MIPI termination in the device. For Virtex-7, you would need to use an external phy as mentioned in xapp894.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: A solution to a 16-lane CSI-2 application

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Thank you for your reply. It helps a lot. I also notice that Ultrascale+ FPGAs have both D-PHY and CSI-2 controller. Virtex-7 FPGAs just supply CSI-2 controller. We will evaluate both Virtex Ultrascale+ and Virtex 7.

I still have another question. The 4 front end radar sensors need to be highly synchronized. If we use four CSI-2 controller to receive the 16-lane data, whether it will influence the system synchronization accuracy or not? Or some specific considerations should be taken?

Thank you.

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Re: A solution to a 16-lane CSI-2 application

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HI @yingliuysy,

The D-PHY IP should available in both Virtex-7 and Ultrascale+ (in fact it is use by the MIPI CSI2 RX IP).

What I am talking is really the termination. Only Ultrascale+ devices have a MIPI_PHY_DCI termination on the IOs (refer to DS922)

mipi.JPG

About the synchronization, you will have to handle it in your code but it should be doable.

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: A solution to a 16-lane CSI-2 application

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Hi @florentw,

I see the datasheet of XAPP894 and DS922. Maybe I get your point and I had some misunderstanding. So the main work of XAPP894 is to convert the FPGA I/O standard to comply with the D-PHY standard, right? And this is necessary for Virtex 7 FPGAs. If we choose Ultrascale+ FPGAs, the I/O banks can support D-PHY standard originally, as shown in the table. Both low power (LP) and high speed (HS) I/O standards are supported.

Regards.

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Re: A solution to a 16-lane CSI-2 application

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Hi @yingliuysy,

Yes this is correct


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**