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Observer
Observer
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Registered: ‎05-07-2018

AXI Stream Video encoding

Hey guys,

I am a little confused about the TDATA pixel mapping when trasmitting video data over AXI4-Stream interface. Below are two chunks of two different documents, where the descriptions are kinda opposite to one another:

ug934.PNG

The first one is more recent and states that the active data bits should be MSB aligned.

ug1037.PNG

According to the second document the data should be LSB aligned.

 

Which configuration should be considered correct?

Regards,
Rosi

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Moderator
Moderator
361 Views
Registered: ‎11-09-2015

Hi @hawthorn_3 

The Xilinx video IPs are following the UG934. Please consider it as the most up to date.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @hawthorn_3 

Updated: I have aksed the section "Video IP: AXI Feature Adoption" to be removed from UG1037. This should just point to UG934 which is kept up to date


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**