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Explorer
Explorer
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Registered: ‎04-19-2016

AXI Stream sides back-to-back connected VDMAs

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Hello,

 

I have two VDMAs in my design where one is MM2S (Read) mode, and the other one is S2MM (write) mode. Axi-Stream ports of them connected to each-other like this;

 

MM2S <-->S2MM

 

In the Zynq, each VDMA can reach to both PS DDR3 (through HP) and PL DDR3. Thus, I think that I can directly transfer data from PS DDR3 to PL DDR3, or vice-versa by using these two VDMAs. (analogoues to memcpy function in SW)

 

I have configured S2MM VDMA firstly, then configured the MM2S VDMA. I can do above transfers but with some errors. Some data is missed sometimes. When I increase the transferred data, errors will also increase. Why is this error coming from? Connection of two VDMA Axi-Stream ports is problematic case?

 

Best Regards,

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Moderator
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Registered: ‎11-09-2015

Hi @doner_t,

 

How are you synchronizing both VDMA? My guess is that you are writing in the same VDMA you are reading to.

 

You should start by increasing the number of buffer for both VDMA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎10-04-2017

Hi @doner_t,

 

If I am correct, you are trying to read data from PS memory and then write it back into PL memory using 2 VDMA's. I believe that this is a valid use case but there are several things that need to be considered.

 

 

Before moving forward can you clarify the following?

 

1. When you say errors, can you explain what type of errors you are seeing?

2. What are the clock speeds of the 2 VDMAs?

3. How are you configuring the VDMAs?

4. What are the transfer speeds?

5. What version of the firmware/tools are you using?

6. Have you looked at the Hardware Debug section of PG020?

 

Regards,

Sam

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Explorer
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Registered: ‎04-19-2016

Hello @samk,

 

1. When you say errors, can you explain what type of errors you are seeing?

When I transfer data from PS DDR3 to PL DDR3 (assume a 100x100 picture pixels), some of the pixels are seen as 0 (zero) after transfer completed, other pixels are not corrupted. These errors are seen even data transfer from one area of PS DDR3 to another area of PS DDR3 using these two back-to-back connected VDMAs path. 

 

2. What are the clock speeds of the 2 VDMAs?

Both VDMAs AXIS side and AXI (memory-mapped side) clocks are the same which is 200MHz.

 

3. How are you configuring the VDMAs?

HW side configurations;

Read VDMA (MM2S);

*frame buffer:1

*memory map data width:32

*read burst size:256

*stream data width:32

*line buffer depth:128

*fsync options:none

*genlock mode:master

*allow unaligned transfer:ticked

 

Write VDMA (S2MM);

*frame buffer:1

*memory map data width:32

*write burst size:256

*stream data width:32

*line buffer depth:128

*fsync options:none

*genlock mode:master

*allow unaligned transfer:ticked

 

SW side configurations;

HSIZE ve VSIZE and Stride values are configured, then waiting interrupt. After interrupt are received, S2MM and MM2S channels are enabled, respectively.

 

Could you explain the interrupt routine of VDMA for this configuration parameters? i.e: when will interrupt be generated?   

 

4. What are the transfer speeds?

Is it configured in SW side? I dont know any parameter in HW related transfer speed.

 

 5.What version of the firmware/tools are you using?

Vivado 2016.3 and VDMAs in 6.2 version

 

6. Have you looked at the Hardware Debug section of PG020?

Sure. Not found a proper solution. 

 

Best Regards,

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Moderator
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Registered: ‎11-09-2015

Hi @doner_t,

 

How are you synchronizing both VDMA? My guess is that you are writing in the same VDMA you are reading to.

 

You should start by increasing the number of buffer for both VDMA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
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Registered: ‎04-19-2016

@florentw,

 

There is currently no any synchronizing mechanism between two VDMAs.  Only Axi-Stream ports are connected to each other. There are two seperate VDMAs where one is only for writing(S2MM) and the other one is only reading(MM2S). At first, I have tried this schema with only one VDMA as you guess. 

 

I will update after trying increasing the frame buffer number.

 

Best Regards,

 

 

 

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Registered: ‎11-09-2015

Hi @doner_t,

 

Do you have any updates on this?

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
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Registered: ‎04-19-2016

Dear @florentw,

 

Please sorry for delay, I was out of office. I have already tried increasing the Frame buffer number. But missed data is also increased. I decided to give up these back-to-back connected VDMAs architecture. I have to directly reach  to PL DDR3 through one of PS Master AXI ports. 

 

Best Regards,

 

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