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Contributor
Contributor
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Registered: ‎12-10-2018

AXI VDMA EOL Late and SOF Early Errors

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Hello!

I'm using AXI VDMA IP-Core in my design. I use a 720p video for testing, and I check the input to the core. I use some counters and ILAs to analyze the input. I count the number of lines by counting the number of tlasts occured at the input and reset this counter at the rising edge of tuser which shows a new frame is started. And for the width I use ILA to see the distance between a tuser and a tlast, or between two consecutive tlasts. The input width is 1280 and the height is 720. But when I read the S2MM_VDMASR register, I see there's EOL Late and SOF Early errors. I do not know why this ocuurs, because I have checked the input precisely and there are corrct number of pixels and lines at the input.

In my output video, there are errors and the video has some bounces which shows there's something wrong. I have tried many ways and I could not solve or find the root of the problem. Can anybody help me with this? Any help is highly appreciated!

Regards,

Herman

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Moderator
Moderator
345 Views
Registered: ‎10-04-2017

How many pixels per clock is your input stream?

If you have 2ppc, then you should only count 1/2 the number of clocks per line.

 

**Also, make sure your AXI4-Stream master is sending the video correctly. It should confirm to UG934

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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Teacher
Teacher
376 Views
Registered: ‎06-16-2013

Hi @hermanfisher1994 

 

Did you make sure and consider clock frequency ?

Were they proper clock freqency ?

 

Best regards,

Moderator
Moderator
346 Views
Registered: ‎10-04-2017

How many pixels per clock is your input stream?

If you have 2ppc, then you should only count 1/2 the number of clocks per line.

 

**Also, make sure your AXI4-Stream master is sending the video correctly. It should confirm to UG934

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post