07-09-2020 05:49 AM - edited 07-09-2020 06:17 AM
I have a design where I utilized a VDMA IP. I have almost a nice output but I can see that some pixels are shifted. I have a doubt about the latency of the VDMA since I couldn't see a problem related to other IPs. Should I think about the latencies that is provided below during coding? I have chosen fsync as "s2mm_tuser" for write channel and "none" for read channel. Right now, I am writing to the VSIZE registers immediately and not waiting for these latencies. If I should consider these, I couldn't get how I am supposed to do that. Can you give a guidance? (at some point, I rewrite new values to the registers of VDMA since resolution changes)
Thank you for your time.
07-09-2020 06:32 AM
In my experience, "shifted pixels" are not caused by VDMA latency. It's more typically a result of a mismatch somewhere in the processing. Make sure that your "Tuser" and "Tlast" signals are being handled correctly through out the processing pipeline.
As for the VDMA:
07-13-2020 05:06 AM
07-13-2020 06:10 AM
From you previous post, it sounds like you are using both Rd and Wr VDMA channels. Are they "Gen-Locked"? If so which one is the master? When changing resolution sizes, do you have to change the resolution size in any other IP? If so, do any of those IP have to "lock" to the new resolution? The "Video_In_to_AXI4_Stream" IP has to relock when the resolution changes. That "relock" can take several frames. Do you have an external input source like a camera that has to change resolution? Updating a camera can be hard to do quickly.
I would recommend just looking at the display section of the design first. See if you can smoothly transition the display without the video input section running. Once that works well, then look at doing the same with just the input section. Once it works well then try both together. There may be some kind of momentary memory contention that happens when the transition happens.