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z.iqbal
Visitor
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Registered: ‎06-20-2018

AXI VDMA Software Program

Hello guys,

 

I have a project in which I have used AXI VDMA. As a beginner of VDMA, I started with test bench. 

After that I have started with test program in C-code. from the Video Series of AXI VDMA by @florentw, I have programmed the VDMA Read and Write Registers directly. It works with free run mode and working fine.

My block design in Vivado is in attachment. Initially, I have written some Pattern/Data in memory. Then Start the VDMA MM2S to Read from memory address and writes into Stream Data FIFO. Whenever my Video IP is ready then it receives the data from FIFO. But for the verification of I am sending back data to another FIFO which is attached to S2MM side of VDMA. The VDMA writes the Data into another address of memory. 

 
 

 

But now I want to make a program that can run with specific number of frames and then stops. I have good skills in VHDL but not with C-language. From the Vivado directory I found a example code of VDMA i.e. xaxivdma_example_intr.c which I have used in my project and it also works with free run mode means continuosly reading data from memory after specified number of VSize.

In one post, Someone told that for specific number of frames one have to use XAxiVdma_FrameCount, XAxiVdma_SetFrameCounter() and XAxiVdma_StartFrmCntEnable() but due to lack of experience in C, I don't know how to edit this code.

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-VDMA-Stopping-at-the-end-of-a-frame/m-p/697851#M17599

 

Could someone here to help me regarding test Program of VDMA.

 

Thanks

Zeeshan

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z.iqbal
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Registered: ‎06-20-2018

Hi,

one more thing that confuse me is Frame buffer and number of Pages are same or it's different. In my design I have used 3 buffers.

For example, I need to send a Page (in which data has to print) to my VideoIP. So same page I have to send number of times to my IP. So, for that purpose I need to configure Frame buffer of some thing else.

Thanks

Regards,

Zeeshan

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z.iqbal
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Registered: ‎06-20-2018

Hello guys,

I have some how edit the Test Program in C and include the XAxiVdma_SetFrameCounter() and XAxiVdma_StartFrmCntEnable() functions. After checking the MM2S Control Register, the VDMA Stops after 3 frames but I got Error EolLateErr in Write side. When I checked in ILA core then I found that the FIFO_tlast which is connected to my VideoIP, is still high. Even though I have read the last byte in FIFO. The Rd_Data_Count also shows 0 which means nothing data left for reading side.

Could anyone please tell me the reason or give some tips.

Thanks

Regards

Zeeshan

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florentw
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Registered: ‎11-09-2015

Hi @z.iqbal 

First note that the AXI VDMA includes an example design which is doing pretty much what you are trying to achieve (not using C code but an AXI trafic generator). It might worth for you to have a look.

Then it would be great if you could share the ILA capture because this is hard to say without really seeing what is happening. TLAST might stay high if tvalid is low.

I am not sure what you mean by "Pages"


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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