cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
abady1000
Visitor
Visitor
315 Views
Registered: ‎11-01-2020

AXI VDMA add zeros when writing to DDR

I have vivado 2018.2, and I am using PYNQ-Z2 board

 

I generate images of size 640*512 using Test Pattern Generator, and move these images to RAM using VDMA then read only size of 640*480, so I crop 32 lines from the bottom. This simple hardware worked with me, I dont know what changed, but today it generate the images wrongly, an organized black columns are added in the middle of the images in specific places, I debug looking for errors and what I found is that in VDMA write channel data is sent as I expected, but in read channel there are 32 new bits added after every 32 bit of my data.

 

wondering if any one encountered a similar problem or know hoe to fix the problem.

 

problem.jpg

 

Here is where the problem started

 

Screenshot from 2020-11-10 14-40-57.png

And here where I found the problem, in M_AXI_S2MM write channel you can see clearly that data is always the same, but in M_AXI_MM2S read channel data there are 32 bit zero added after every 32 bit

NOTE: write channel is 64bit, but read channel is 32bit, I tried to make it 64but but the problem still last.

Tags (1)
0 Kudos
2 Replies
Nikhil_Thapa
Explorer
Explorer
248 Views
Registered: ‎05-28-2020

Hi @abady1000 ,

NOTE: write channel is 64bit, but read channel is 32bit,

What are you trying to say by this line? Are you saying Memory mapped width or Stream data width?

I believe you are referring Stream data width. If so, then you must understand that when write stream width is 64 bit wide (>32 bit), then two DDR memory addresses will be used to store 64 bit data. Your 64 bit data is divided into two (32-32 bit). In case of read channel, when it is 32 bit wide, it always reads 32 bit data from each DDR memory location. Your 64 bit data is read twice.

You also need to check stride value. Looks like your 64 bit data is not written correctly into the DDR memory. Therefore, VDMA is reading first half data correctly and second half data as zeros.

You can use read XSCT commands to check whether data is correctly written or not into DDR memory.

If you want to have detail information about VDMA design, you can follow the tutorials below

Video Series 24: Using the AXI VDMA in Triple Buff... - Community Forums 

Video Series 25: Debugging issues on the AXI VDMA ... - Community Forums 

Video Series 26: Examples of advanced uses of the ... - Community Forums 

I also recommend to check Video Series 26 because you are doing cropping operation.

Regards,

nikhil@logictronix.com
:::::Do not forget to Accept as solution, give Kudo and Share a post that you think is helpful:::::
Nikhil_Thapa
Explorer
Explorer
171 Views
Registered: ‎05-28-2020

Hi @abady1000 ,

Did you solve your issue? Let me know. Otherwise, you can close the thread by accepting the solution.

 

Regards,

nikhil@logictronix.com
:::::Do not forget to Accept as solution, give Kudo and Share a post that you think is helpful:::::
0 Kudos