AXI4-Stream to Video out not producing any output signals

[rishubnagpal]

Hi,

My target board is the Nexys 4 DDR, and my desired Video resolution is 640x480p

I have a design with the following video pipeline:

V_TPG -> VDMA -> AXI4-Stream to Video out

I have a VTC to provide the timing for the Video Out side. The VTC and AXi-Video Out are both driven by a 25 Mhz clock. Here is a picture of my setup:

Again, Vid_io_clk and the VTC clk are driven by a 25Mhz clock.

Gen_clken and vtg_ce are connected

aclken, vi_io_out_ce, clken, resetn are all connected to logic 1

I have inserted ILAs and can confirm that the VTC is transmitting the correct timing (vsync, blanks) and the video_in port is reviving valid data.

Here are my configs for each component and ILA outputs. Please let me know if I am missing something

 

 

 

 

This is the ILA output of the VTC

This is the output of the AXIS4 Stream to Video out.

This is the output of the VDMA read side i.e. Video In to the AXI4s - Video out IP

And finally, here is the code I am running to initialize everything. I am using the vdma_api.c example file to init the VDMA found here

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xv_tpg.h"
#include "xaxivdma.h"

XV_tpg_Config *tpg_config;
XV_tpg tpg;
XAxiVdma vdma;



int main()
{
    init_platform();
    int status;

    tpg_config = XV_tpg_LookupConfig(XPAR_V_TPG_0_DEVICE_ID);
	if(tpg_config == NULL)
	{
		xil_printf("ERR:: TPG device not found\r\n");
		return(XST_DEVICE_NOT_FOUND);
	}
	status = XV_tpg_CfgInitialize(&tpg, tpg_config, tpg_config->BaseAddress);
	if(status != XST_SUCCESS)
	{
		xil_printf("ERR:: TPG Initialization failed %d\r\n", status);
		return(XST_FAILURE);
	}
	XV_tpg_Set_height(&tpg, 480);
	XV_tpg_Set_width(&tpg, 640);

	XV_tpg_EnableAutoRestart(&tpg);
	XV_tpg_Start(&tpg);

    print("Hello World\n\r");
	status = run_triple_frame_buffer(&vdma, 0, 640, 480,
			XPAR_MIG_7SERIES_0_BASEADDR, 100, 0);

	if (status != XST_SUCCESS) {
		xil_printf("Transfer of frames failed with error = %d\r\n",status);
		return XST_FAILURE;
	} else {
		xil_printf("Transfer of frames started \r\n");
	}
    cleanup_platform();
    return 0;
}

I have also exported the block design and attached the TCL file below

Please let me know if more information is needed! 

[watari · Accepted solution]

Hi @rishubnagpal

I suggest to make sure the followings.

- aresetn, vid_io_out_reset and fid are open on axi4s-to-vid-out. Connect them.

- Make sure intc_if's value on v_tc. It is helpful for debugging.

- Also, make sure status value on axi4s-to-vid-out.

Would you try it ?

Best regards,

[rishubnagpal]

@watari

I set fid, vid_reset and field_id to ground (logic 0)

I set aresetn to VCC (logic 1) and AXI4 stream to Master mode

I was able to get the video to display and lock

Thanks!